ADBF539WBBCZ5 View Datasheet(PDF) - Analog Devices

Part Name

Description

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ADBF539WBBCZ5

Blackfin Embedded Processor

Analog Devices 

ADSP-BF539/ADSP-BF539F

The PC133-compliant SDRAM controller can be programmed

to interface to up to 128M bytes of SDRAM. The SDRAM con-

troller allows one row to be open for each internal SDRAM

bank, for up to four internal SDRAM banks, improving overall

system performance.

The asynchronous memory controller can be programmed to

control up to four banks of devices with very flexible timing

parameters for a wide variety of devices. Each bank occupies a

1M byte segment regardless of the size of the devices used, so

that these banks will only be contiguous if each is fully popu-

lated with 1M byte of memory.

Flash Memory (ADSP-BF539F Only)

The ADSP-BF539F8 processor contains a separate flash die,

connected to the EBIU bus, within the package of the processor.

Figure 4 shows how the flash memory die and Blackfin proces-

sor die are connected.

The ADSP-BF539F8 contains an 8M bit (512K × 16-bit) bottom

boot sector Spansion S29AL008J known good die flash memory.

Additional information for this product can be found in the

Spansion data sheet at www.spansion.com. Features include the

following:

• Access times as fast as 70 ns (EBIU registers must be set

appropriately)

• Sector protection

• One million write cycles per sector

• 20 year data retention

ADDR19-1

ARE

AWE

ARDY

DATA15-0

GND

VDDEXT

AMS3-0

RESET

B

ADSP-BF539F

PACKAGE

A18-0

OE

WE

RY/BY

DQ15-0

VSS

VCC

BYTE

CE

RESET

WP

Figure 4. Internal Connection of Flash Memory (ADSP-BF539F8)

The Blackfin processor connects to the flash memory die with

address, data, chip enable, write enable, and output enable con-

trols as if it were an external memory device. Note that the

write-protect input pin to the flash is not connected and inac-

cessible, disabling this feature.

The flash chip enable pin FCE must be connected to AMS0 or

AMS3–1 through a printed circuit board trace. When connected

to AMS0, the Blackfin processor can boot from the flash die.

When connected to AMS3–1, the flash memory appears as non-

volatile memory in the processor memory map, shown in

Figure 3.

Flash Memory Programming

The ADSP-BF539F8 flash memory can be programmed before

or after mounting on the printed circuit board.

To program the flash prior to mounting on the printed circuit

board, use a hardware programming tool that can provide the

data, address, and control stimuli to the flash die through the

external pins on the package. During this programming, VDDEXT

and GND must be provided to the package and the Blackfin

must be held in reset with bus request (BR) asserted and a

CLKIN provided.

The VisualDSP++ tools can be used to program the flash mem-

ory after the device is mounted on a printed circuit board.

Flash Memory Sector Protection

To use the sector protection feature, a high voltage (+8.5 V to

+12.5 V) must be applied to the flash FRESET pin. Refer to the

flash data sheet for details.

I/O Memory Space

Blackfin processors do not define a separate I/O space. All

resources are mapped through the flat 32-bit address space. On-

chip I/O devices have their control registers mapped into mem-

ory mapped registers (MMRs) at addresses near the top of the

4G byte address space. These are separated into two smaller

blocks, one of which contains the control MMRs for all core

functions, and the other of which contains the registers needed

for setup and control of the on-chip peripherals outside of the

core. The MMRs are accessible only in supervisor mode and

appear as reserved space to on-chip peripherals.

Booting

The ADSP-BF539/ADSP-BF539F processors contain a small

boot kernel, which configures the appropriate peripheral for

booting. If the processors are configured to boot from boot

ROM memory space, they start executing from the on-chip boot

ROM. For more information, see Booting Modes on Page 16.

Event Handling

The event controller handles all asynchronous and synchronous

events to the processor. The processors provide event handling

that supports both nesting and prioritization. Nesting allows

multiple event service routines to be active simultaneously. Pri-

oritization ensures that servicing of a higher priority event takes

precedence over servicing of a lower priority event. The control-

ler provides support for five different types of events:

• Emulation – An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

• Reset – This event resets the processor.

Rev. F | Page 6 of 60 | October 2013

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