M5M51R16AWG-15HI View Datasheet(PDF) - MITSUBISHI ELECTRIC
Part Name
Description
View to exact match
M5M51R16AWG-15HI Datasheet PDF : 7 Pages
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Write cycle ( BC1, BC2 control mode )
A 0~15
MITSUBISHI LSIs
M5M51R16AWG -10LI, -12LI, -15LI,
-10HI, -12HI, -15HI
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
tCW
BC1 and/or BC2
tsu(A)
tsu(BC1) or
tsu(BC2)
trec(W)
S
W
DQ1~16
(Note 4)
(Note 6)
(Note 4)
(Note 5)
tsu(D) th(D)
DATA IN
STABLE
Write cycle (S control mode)
tCW
A 0~15
(Note 4)
(Note 4)
BC1 and/or BC2
S
W
DQ1~16
(Note 4)
tsu(A)
(Note 6)
(Note 4)
tsu(S)
trec(W)
(Note 5)
tsu(D) th(D)
DATA IN
STABLE
(Note 4)
(Note 4)
Aug.1. 1998
Note 4: Hatching indicates the state is "don't care".
Note 5: Writing is executed while S low overlaps BC1 and/or BC2 low and W low.
Note 6: When the falling edge of W is simultaneously or prior to the falling edge of BC1 and/or BC2
or falling edge of S, the outputs are maintained in the high impedance state.
Note 7:Don't apply inverted phase signal externally when DQ pin is output mode.
Note 8:ten,tdis are periodically sampled and are not 100% tested.
Note 9:tCR(Read cycle time) is defined as whole time from reading address set up to this address change
under read mode set condition by S,W,OE,BC1 and/or BC2.
Note 10:tCW(Write cycle time) is defined as whole time from writing address set up to this address change
under write mode set condition by S,W,BC1 and/or BC2.
MITSUBISHI
ELECTRIC
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