CY7C1041BNV33L-12ZXC(2011) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
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CY7C1041BNV33L-12ZXC Datasheet PDF : 14 Pages
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Switching Characteristics[4]
Over the Operating Range
Parameter
Description
READ CYCLE
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE
tHZBE
WRITE CYCLE[7, 8]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tBW
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[5, 6]
CE LOW to Low Z[6]
CE HIGH to High Z[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
WE LOW to High Z[5, 6]
Byte Enable to End of Write
CY7C1041BNV33
-12
Unit
Min
Max
12
–
ns
–
12
ns
3
–
ns
–
12
ns
–
6
ns
0
–
ns
–
6
ns
3
–
ns
–
6
ns
0
–
ns
–
12
ns
–
6
ns
0
–
ns
–
6
ns
12
–
ns
10
–
ns
10
–
ns
0
–
ns
0
–
ns
10
–
ns
7
–
ns
0
–
ns
3
–
ns
–
6
ns
10
–
ns
Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. tfHroZmOEs,tteHaZdCyE-,satantde tvHoZltWaEgea.re specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms on page 4. Transition is measured ±500 mV
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 001-06434 Rev. *C
Page 5 of 14
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