ADN2812ACP View Datasheet(PDF) - Analog Devices
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Description
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ADN2812ACP
Analog Devices
ADN2812ACP Datasheet PDF : 28 Pages
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ADN2812
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 223 − 1,
unless otherwise noted.
Table 1.
Parameter
QUANTIZER—DC CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Input Common Mode Level
Differential Input Sensitivity
Input Overdrive
Input Offset
Input RMS Noise
QUANTIZER—AC CHARACTERISTICS
Data Rate
S11
Input Resistance
Input Capacitance
QUANTIZER—SLICE ADJUSTMENT
Gain
Differential Control Voltage Input
Control Voltage Range
Slice Threshold Offset
LOSS OF SIGNAL DETECT (LOS)
Loss of Signal Detect Range (see Figure 5)
Hysteresis (Electrical)
LOS Assert Time
LOS De-Assert Time
LOSS OF LOCK DETECT (LOL)
VCO Frequency Error for LOL Assert
VCO Frequency Error for LOL De-Assert
LOL Response Time
ACQUISITION TIME
Lock to Data Mode
Optional Lock to REFCLK Mode
Conditions
Min
@ PIN or NIN, dc-coupled
1.8
PIN – NIN
DC-coupled (see Figure 28, Figure 29,
and Figure 30)
2.3
223 − 1 PRBS, ac-coupled,1 BER = 1 x 10–10 10
(see Figure 12)
5
BER = 1 x 10–10
12.3
@ 2.5 GHz
Differential
SLICEP – SLICEN = ±0.5 V
SLICEP – SLICEN
DC level @ SLICEP or SLICEN
0.08
–0.95
VEE
RThresh = 0 Ω
12
RThresh = 100 kΩ
2.0
OC-48
RThresh = 0 Ω
5.6
RThresh = 100 kΩ
3.7
OC-1
RThresh = 0 Ω
5.6
RThresh = 10 kΩ
2.0
DC-coupled2
DC-coupled2
With respect to nominal
With respect to nominal
12.3 Mb/s
OC-12
OC-48
OC-48
OC-12
OC-3
OC-1
12.3 Mb/s
Typ
2.5
6
3
500
290
−15
100
0.65
0.1
1
15
3.0
6
6
6
4
500
400
1000
250
4
1.0
1.0
1.3
2.0
3.4
9.8
40.0
10.0
Max
2.8
2.0
2.8
2700
0.12
+0.95
0.95
17
4.0
7.2
8.4
7.2
6.7
Unit
V
V
V
mV p-p
mV p-p
µV
µV rms
Mb/s
dB
Ω
pF
V/V
V
V
mV
mV
mV
dB
dB
dB
dB
ns
ns
ppm
ppm
ms
µs
µs
ms
ms
ms
ms
ms
ms
1 PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.
2 When ac-coupled, the LOS assert and de-assert time is dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the
ADN2812 input stage.
Rev. 0 | Page 3 of 28
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