ISL8010 View Datasheet(PDF) - Renesas Electronics
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ISL8010 Datasheet PDF : 11 Pages
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ISL8010
is called a “hiccup” event. The average power dissipation is
reduced, thereby reducing the likelihood of damaged current
and thermal conditions in the IC.
tH
I
CC
U
P
7----0---0------3------V----I--N--
+
216
(EQ. 1)
Thermal Shutdown
Once the junction reaches about +145°C, the regulator shuts
down. Both the P-Channel and the N-Channel MOSFETs
turn off. The output voltage will drop to zero. With the output
MOSFETs turned off, the regulator will cool down. Once the
junction temperature drops to about +130°C, the regulator
will perform a normal restart.
Thermal Performance
The ISL8010 is available in a fused-lead 10 Ld MSOP
package. Compared with regular 10 Ld MSOP package, the
fused-lead package provides lower thermal resistance. The
JA is +100°C/W on a 4-layer board and +125°C/W on
2-layer board. Maximizing the copper area around the pins
will further improve the thermal performance.
Power Good Output
The PG (pin 8) output is used to indicate when the output
voltage is properly regulating at the desired set point. It is an
open-drain output that should be tied to VIN or VCC through
a 100k resistor. If no faults are detected, EN is high, and
the output voltage is within ~5% of regulation, the PG pin will
be allowed to go high. Otherwise, the open-drain NMOS will
pull PG low.
Output Voltage Selection
Users can set the output voltage of the variable version with
a resistor divider, which can be chosen based on Equation 2:
VO
=
0.8
1
+
R-R----12-
(EQ. 2)
Component Selection
Because of the fixed internal compensation, the component
choice is relatively narrow. For a regulator with fixed output
voltage, only two capacitors and one inductor are required. It
is recommended to use between 10µF and 22µF multilayer
ceramic capacitors with X5R or X7R rating for both the input
and output capacitors, and 1.5µH to 2.2µH for the inductor.
The RMS current present at the input capacitor is decided by
Equation 3:
IINRMS = -----V----O----------V---V--I--NI--N-----–-----V----O----- IO
(EQ. 3)
This is about half of the output current IO for all the VO. This
input capacitor must be able to handle this current.
The inductor peak-to-peak ripple current is given as
Equation 4:
IIL = ---V----LI--N------–--V--V--I--N-O---------f--S--V----O--
(EQ. 4)
L is the inductance
fS is the switching frequency (nominally 1.4MHz)
The inductor must be able to handle IO for the RMS load
current, and to assure that the inductor is reliable, it must
handle the 2A surge current that can occur during a current
limit condition.
In addition to decoupling capacitors and inductor value, it is
important to properly size the phase-lead capacitor C4
(Refer to “Typical Application Diagram” on page 1). The
phase-lead capacitor creates additional phase margin in the
control loop by generating a zero and a pole in the transfer
function. As a general rule of thumb, C4 should be sized to
start the phase-lead at a frequency of ~2.5kHz. The zero will
always appear at lower frequency than the pole and follow
Equation 5:
fZ = 2--------R--1---2---C-----4-
(EQ. 5)
Over a normal range of R2 (~10kto 100k), C4 will range
from ~470pF to 4700pF. The pole frequency cannot be set
once the zero frequency is chosen as it is dictated by the
ratio of R1 and R2, which is solely determined by the desired
output set point. Equation 6 shows the pole frequency
relationship:
fP = -2----------R----1----1----R----2------C-----4-
(EQ. 6)
Layout Considerations
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
1. Separate the Power Ground ( ) and Signal Ground
( ); connect them only at one point right at the pins
2. Place the input capacitor as close to VIN and PGND pins
as possible
3. Make the following PC traces as small as possible:
- from LX pin to L
- from CO to PGND
4. If used, connect the trace from the FB pin to R1 and R2
as close as possible
5. Maximize the copper area around the PGND pin
6. Place several via holes under the chip to additional
ground plane to improve heat dissipation
The demo board is a good example of layout based on this
outline. Please refer to the ISL8010 Application Note.
FN6191 Rev 6.00
October 18, 2010
Page 10 of 11
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