HM62W8512BI Series
Low VCC Data Retention Characteristics (Ta = –40 to +85°C)
Parameter
Symbol Min Typ Max Unit Test conditions*2
VCC for data retention
Data retention current
VDR
I CCDR
2
——
V
— 0.8*3 20*1 µA
CS ≥ VCC – 0.2 V, Vin ≥ 0 V
VCC = 3.0 V, Vin ≥ 0 V
CS ≥ VCC – 0.2 V
Chip deselect to data retention time tCDR
0
——
ns
See retention waveform
Operation recovery time
tR
tRC*4 —
—
ns
Notes: 1. For L-version and 10 µA (max.) at Ta = –40 to +40°C.
2. CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin
levels (address, WE, OE, I/O) can be in the high impedance state.
3. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
4. tRC = read cycle time.
Low VCC Data Retention Timing Waveform (CS Controlled)
tCDR
Data retention mode
tR
VCC
3.0 V
2.4 V
VDR
CS
0V
CS ≥ VCC – 0.2 V
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