SL74HC161N View Datasheet(PDF) - System Logic Semiconductor
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SL74HC161N Datasheet PDF : 9 Pages
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SL74HC161
TYPICAL APPLICATIONS CASCADING
Note:When used in these cascaded configurations the clock fmax guaranteed limits may not apply.
Actual performance will depend on number of stages. This limitation is due to set up times
between Enable (Port) and clock.
Figure 9. N-Bit Synchronous Counters
Figure 10. Nibble Ripple Counter
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