PD45128163G5-A10LI-9JF View Datasheet(PDF) - Elpida Memory, Inc

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PD45128163G5-A10LI-9JF

128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

Elpida Memory, Inc 

µPD45128441-I, 45128841-I, 45128163-I

CONTENTS

1. Input / Output Pin Function ........................................................................................................... 10

2. Commands ...................................................................................................................................... 11

3. Simplified State Diagram ............................................................................................................... 14

4. Truth Table ...................................................................................................................................... 15

4.1 Command Truth Table ............................................................................................................................ 15

4.2 DQM Truth Table ..................................................................................................................................... 15

4.3 CKE Truth Table ...................................................................................................................................... 15

4.4 Operative Command Table .................................................................................................................... 16

4.5 Command Truth Table for CKE ............................................................................................................. 19

5. Initialization ..................................................................................................................................... 20

6. Programming the Mode Register .................................................................................................. 21

7. Mode Register ................................................................................................................................. 22

7.1 Burst Length and Sequence ................................................................................................................. 23

8. Address Bits of Bank-Select and Precharge ................................................................................ 24

9. Precharge ........................................................................................................................................ 25

10. Auto Precharge ............................................................................................................................... 26

10.1 Read with Auto Precharge .................................................................................................................. 26

10.2 Write with Auto Precharge ................................................................................................................. 27

11. Read / Write Command Interval .................................................................................................... 28

11.1 Read to Read Command Interval ....................................................................................................... 28

11.2 Write to Write Command Interval ....................................................................................................... 28

11.3 Write to Read Command Interval ....................................................................................................... 29

11.4 Read to Write Command Interval ....................................................................................................... 30

12. Burst Termination ........................................................................................................................... 31

12.1 Burst Stop Command ......................................................................................................................... 31

12.2 Precharge Termination ....................................................................................................................... 32

12.2.1 Precharge Termination in READ Cycle ................................................................................... 32

12.2.2 Precharge Termination in WRITE Cycle ................................................................................. 33

8

Preliminary Data Sheet E0233N10

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