HTG12B0 View Datasheet(PDF) - Holtek Semiconductor

Part Name

Description

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HTG12B0

4-Bit Microcontroller

Holtek Semiconductor 

HTG12B0

R A M B ank 0

(R A M B = X 0 0 0 B )

R A M B ank 1

(R A M B = X 0 0 1 B )

00H

T e m p o ra ry D a ta A re a

00H

T e m p o ra ry D a ta A re a

(1 2 8 x 4 )

(1 2 8 x 4 )

7FH

7FH

4 b its

4 b its

R A M B ank 7

(R A M B = X 1 1 1 B )

00H

T e m p o ra ry D a ta A re a

(1 2 8 x 4 )

7FH

4 b its

Temporary data memory

Stack register

The stack register is a group of registers used to

save the contents of the program counter (PC)

and is arranged into 13 bits ´ 1 level. One bit is

used to store the carry flag. An interrupt will

force the contents of the PC and the carry flag

onto the stack register. A subroutine call will

also cause the PC contents to be pushed onto

the stack; however the carry flag will not be

stored. At the end of a subroutine or an inter-

rupt routine which is signaled by a return in-

struction, RET or RETI restore the program

counter to its previous value from stack regis-

ter. Executing ²RETI² instruction will restore

the carry flag from the stack register, but

²RET² does not.

Working registers - R0, R1, R2, R3, R4

There are five working registers (R0, R1, R2, R3,

R4) usually used to store the frequently accessed

intermediate results. Using the instructions INC

Rn and DEC Rn the working registers can incre-

ment (+1) or decrement (-1). The JNZ Rn (n=0, 1,

4) instruction makes efficient use of the working

registers as a program loop counter. Also the reg-

ister pairs R0,R1 and R2,R3 are used as a data

memory pointer when the memory transfer in-

struction is executed.

Data memory - RAM

The static data memory (RAM) is arranged in

128´4-bit format and is used to store data. All

of the data memory locations are indirectly

addressable through the register pair R1,R0 or

R3,R2; for example MOV A,[R3R2] or MOV

[R3R2],A.

There are two areas in the data memory, the

temporary data area and display data area. Ac-

cess to the temporary data area is from 00H to

7FH of RAM bank 0~RAM bank 7. Access to the

display data area is from B0H to FFH of LCD

bank 0 and bank 1.

There are eight banks for the temporary data

memory in HTG12B0, each bank shown in the

figure can be switched by assigning

RAMB0~RAMB2 (bit 0~bit 2 of RAMB). RAMB

is the RAM bank pointer and can be written

only by executing ²MOV RAMB, A² instruction.

Bit 3 of RAMB is unused bit. Each bank maps to

different area of the data memory.

There are two banks for displaying the data

memory, each bank can be switched by the as-

signment of LCDC0 (bit 0 of LCDC). LCDC is a

control register for LCD application and can be

written only by executing ²MOV LCDC, A² in-

struction.

When data is written into the display data area,

it is automatically read by the LCD driver

which then generates the corresponding LCD

driving signals.

LC D B ank 0

(L C D C = X X X 0 B )

B 0H

D is p la y D a ta A r e a

(8 0 x 4 )

FFH

4 b its

LC D B ank 1

(L C D C = X X X 1 B )

B 0H

D is p la y D a ta A r e a

(8 0 x 4 )

FFH

4 b its

Display data memory

9

September 8, 1999

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