CS51031YD8 View Datasheet(PDF) - Cherry semiconductor

Part Name

Description

View to exact match

CS51031YD8

Fast PFET Buck Controller Does Not Require Compensation

Cherry semiconductor 

Block Diagram

COSC

VCC

CS

VREF

IC

7IC

Oscillator

Comparator

A1

G1

VGATE

Flip-Flop

RQ

VC

RG

VGATE

1.5V

VCC

VCCOK

VREF = 3.3V

G3

IT

2.5V

VREF

3.3V

CS

Comparator

A2

F2

G2 S Q

VFB

Comparator

-

A6

1.25V

+

+

Hold

Off

Comp

-

0.7V

-

Fault

Comp

+

1.15V

G4

CS Charge

Sense

Comparator

A4

RQ

2.3V

PGnd

VFB

IT

IT

55

5

1.5V

2.5V

F1

G5

SQ

Slow Discharge

Flip-Flop

A3

+ Slow Discharge

2.4V

Comparator

Gnd

Figure 1: Block Diagram for CS51031

Circuit Description

Theory of Operation

Control Scheme

The CS51031 monitors and the output voltage to determine

when to turn on the PFET. If VFB falls below the internal

reference voltage of 1.25V during the oscillatorÕs charge

cycle, the PFET is turned on and remains on for the dura-

tion of the charge time. The PFET gets turned off and

remains off during the oscillatorÕs discharge time with the

maximum duty cycle to 80%. It requires 7mV typical, and

20mV maximum ripple on the VFB pin is required to oper-

ate. This method of control does not require any loop sta-

bility compensation.

Startup

The CS51031 has an externally programmable soft start fea-

ture that allows the output voltage to come up slowly, pre-

venting voltage overshoot on the output.

At startup, the voltage on all pins is zero. As VCC rises, the

VC voltage along with the internal resistor RG keeps the

PFET off. As VCC and VC continue to rise, the oscillator

capacitor (COSC ) and the Soft start/Fault Timing capacitor

(CS) charges via internal current sources. COSC gets

charged by the current source IC and CS gets charged by

the IT source combination described by:

( ) ICS = IT -

IT + IT .

55 5

The internal Holdoff Comparator ensures that the external

PFET is off until VCS > 0.7V, preventing the GATE flip-flop

(F2) from being set. This allows the oscillator to reach its

operating frequency before enabling the drive output. Soft

start is obtained by clamping the VFB comparatorÕs (A6)

reference input to approximately 1/2 of the voltage at the

CS pin during startup, permitting the control loop and the

output voltage to slowly increase. Once the CS pin charges

above the Holdoff Comparator trip point of 0.7V, the low

feedback to the VFB Comparator sets the GATE flip-flop

during COSC Õs charge cycle. Once the GATE flip-flop is set,

VGATE goes low and turns on the PFET. When VCS exceeds

4

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