CS5166 View Datasheet(PDF) - Cherry semiconductor

Part Name

Description

View to exact match

CS5166

5-Bit Synchronous CPU Controller with Power-Good and Current Limit

Cherry semiconductor 

Electrical Characteristics: 0˚C < TA < 70˚C; 0˚C < TJ < 125˚C; 8V < VCC < 14V; 2.0V DAC Code

(VID4 = VID3 = VID2 = VID1 =0, VID0 = 1), CGATE(H) = CGATE(L) = 3.3nF, COFF = 330pF, CSS= 0.1µF; Unless otherwise stated.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

s VCC Supply Current

Operating

1V<VFB<VDAC (Max On-Time),

No Loads on GATE(H) and GATE(L)

12

20

mA

s VCC Monitor

Start Threshold

Stop Threshold

Hysteresis

GATE(H) Switching

GATE(H) not switching

Start – Stop

3.75

3.95

4.15

V

3.65

3.87

4.05

V

80

mV

s Error Amplifier

VFB Bias Current

COMP Source Current

COMP CLAMP Voltage

COMP Clamp Current

COMP Sink Current

Open Loop Gain

Unity Gain Bandwidth

PSRR @ 1kHZ

VFB = 0V

COMP = 1.2V to 3.6V; VFB = 1.9V

15

VFB = 1.9V, Adjust COMP voltage

0.85

for Comp current = 60µA

COMP = 0V

0.4

VCOMP=1.2V; VFB=2.2V; VSS > 2.5V

180

Note 1

50

Note 1

0.5

Note 1

60

0.1

1.0

µA

30

60

µA

1.0

1.15

V

1.0

1.6

mA

400

800

µA

60

dB

2

MHz

85

dB

s GATE(H) and GATE(L)

High Voltage at 100mA

Low Voltage at 100mA

Rise Time

Fall Time

GATE(H) to GATE(L) Delay

GATE(L) to GATE(H) Delay

GATE pull-down

Measure VCC –GATE

Measure GATE

1.6V < GATE < (VCC – 2.5V)

(VCC – 2.5V) >GATE > 1.6V

GATE(H)<2V, GATE(L)>2V

GATE(L)<2V, GATE(H)>2V

Resistance to PGnd (Note 1)

1.2

2.0

V

1.0

1.5

V

40

80

ns

40

80

ns

30

65

100

ns

30

65

100

ns

20

50

115

kΩ

s Over Current Detection

Current limit voltage

ISENSE Bias Current

s Fault Protection

SS Charge Time

SS Pulse Period

SS Duty Cycle

VFB = 0V to 3.5V

8V < VCC < 12V + 10%

ISENSE = 2.8V

VFB = 3V, VISENSE = 2.8V

VFB = 3V, VISENSE = 2.8V

(Charge Time/Period) × 100

55

76

130

mV

13

30

50

µA

1.6

3.3

5.0

ms

25

100

200

ms

1.0

3.3

6.0

%

3

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