CS5166GDWR16 View Datasheet(PDF) - Cherry semiconductor

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CS5166GDWR16

5-Bit Synchronous CPU Controller with Power-Good and Current Limit

Cherry semiconductor 

Application Information: continued

and provided that PWRGD is low. It is also required that

the overvoltage condition be present for at least the

PWRGD delay time for the OVP signal to be activated. The

resistor values shown in Figure 15 are for VDAC = +2.8V

(DAC = 10111). The VOVP (overvoltage trip-point) can be

set using the following equation:

VCORE

+5V

5K

15K

R1

56K

R2

Q3

2N3906

( ) VOVP = VBEQ3 1 +

R2

R1

OVP

20K

+5V

Q2

10K

CS5166

2N3904

10K

10K

Q1

PWRGD

2N3906

Figure 15: Circuit to implement a dedicated OVP output using the

CS5166.

Power-Good Circuit

The Power-Good pin (pin 13) is an open-collector signal

consistent with TTL DC specifications. It is externally

pulled -up, and is pulled low (below 0.3V) when the regu-

lator output voltage typically exceeds ± 8.5% of the nomi-

nal output voltage. Maximum output voltage deviation

before Power-Good is pulled low is ± 12%.

Trace 4 = 5V from PC Power Supply (5V/div.)

Trace1 = Regulator Output Voltage (1V/div.)

Trace 2 = Inductor Switching Node (5V/div.)

Figure 13: OVP response to an input-to-output short circuit by immedi-

ately providing 0% duty cycle, crow-barring the input voltage to

ground.

2.825V

Trace 2 - PWRGD (2V/div)

Trace 4 - VOUT (1V/div)

Figure 16: PWRGD signal becomes logic high as VOUT enters -8.5% of

lower PWRGD threshold, VOUT = +2.825V (DAC = 10111).

Trace 4 = 5V from PC Power Supply (2V/div.)

Trace 1 = Regulator Output Voltage (1V/div.)

Figure 14: OVP response to an input-to-output short circuit by pulling

the input voltage to ground.

Trace 1 PWRGD (2V/div)

Trace 4 VFB (1V/div)

Figure 17: Power-Good response to an out of regulation condition.

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