AR0141IRSH00SUEA0D3-GEVK View Datasheet(PDF) - ON Semiconductor
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AR0141IRSH00SUEA0D3-GEVK Datasheet PDF : 48 Pages
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AR0141CS
A camera containing
the HiSPi transmitter
Dp0
Dn0
Dp1
Dn1
Tx
Dp2
PHY0
Dn2
Dp3
Dn3
Cp0
Cn0
A host (DSP) containing
the HiSPi receiver
Dp0
Dn0
Dp1
Dn1
Dp2
Rx
Dn2
PHY0
Dp3
Dn3
Cp0
Cn0
Figure 9. HiSPi Transmitter and Receiver Interface Block Diagram
HiSPi Physical Layer
The HiSPi physical layer has four data lanes and an
associated clock lane. Depending on the sensor operating
mode and data rate, it can be configured to use either 2, 3, or
4 lanes. The PHY will serialize a 12− to 20−bit data word and
transmit each bit of data centered on a rising edge of the
clock, the second on the following falling edge of clock.
Figure 10 shows bit transmission. In this example, the word
is transmitted in order of MSB to LSB. The receiver latches
data at the rising and falling edge of the clock.
TxPost
cp
cn
TxPre
dp
MSB
dn
…
…
LSB
1 UI
Figure 10. Timing Diagram
DLL Timing Adjustment
The AR0141CS includes a DLL to compensate for
differences in group delay for each data lane. The DLL is
connected to the clock lane and each data lane, which acts as
a control master for the output delay buffers. Once the DLL
has gained phase lock, each lane can be delayed in 1/8 unit
interval (UI) steps. This additional delay allows the user to
increase the setup or hold time at the receiver circuits and
can be used to compensate for skew introduced in PCB
design.
Delay compensation may be set for clock and/or data lines
in the hispi_timing register R0x31C0. If the DLL timing
adjustment is not required, the data and clock lane delay
settings should be set to a default code of 0x000 to reduce
jitter, skew, and power dissipation.
delay
delay
delay
delay
delay
data _lane 0 data _lane 1
clock_lane 0 data _lane 2 data _lane 3
Figure 11. Block Diagram of DLL Timing Adjustments
www.onsemi.com
11
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