SST89V516RD2-33-C-TQJE View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
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SST89V516RD2-33-C-TQJE Datasheet PDF : 81 Pages
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FlashFlex MCU
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
SPI Control Register (SPCR)
Location
D5H
7
SPIE
6
SPE
5
DORD
4
MSTR
3
CPOL
2
CPHA
1
SPR1
Data Sheet
0
SPR0
Reset Value
00H
Symbol
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1, SPR0
Function
If both SPIE and ES are set to one, SPI interrupts are enabled.
SPI enable bit.
0: Disables SPI.
1: Enables SPI and connects SS#, MOSI, MISO, and SCK to pins P1.4, P1.5, P1.6, P1.7.
Data Transmission Order.
0: MSB first in data transmission.
1: LSB first in data transmission.
Master/Slave select.
0: Selects Slave mode.
1: Selects Master mode.
Clock Polarity
0: SCK is low when idle (Active High).
1: SCK is high when idle (Active Low).
Clock Phase control bit. The CPHA bit with the CPOL bit control the clock and data
relationship between master and slave. See Figures 1 and 6-5.
0: Shift triggered on the leading edge of the clock.
1: Shift triggered on the trailing edge of the clock.
SPI Clock Rate Select bits. These two bits control the SCK rate of the device
configured as master. SPR1 and SPR0 have no effect on the slave. The relationship
between SCK and the oscillator frequency, fOSC, is as follows:
SPR1
0
0
1
1
SPR0
0
1
0
1
SCK = fOSC divided by
4
16
64
128
SPI Status Register (SPSR)
Location
7
6
5
4
3
2
1
AAH
SPIF
WCOL
-
-
-
-
-
Symbol
SPIF
WCOL
Function
SPI Interrupt Flag.
Upon completion of data transfer, this bit is set to 1.
If SPIE =1 and ES =1, an interrupt is then generated.
This bit is cleared by software.
Write Collision Flag.
Set if the SPI data register is written to during data transfer.
This bit is cleared by software.
0
Reset Value
-
00xxxxxxb
©2007 Silicon Storage Technology, Inc.
29
S71273-03-000
1/07
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