MT8804A View Datasheet(PDF) - Zarlink Semiconductor Inc
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MT8804A Datasheet PDF : 9 Pages
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MT8804A CMOS
MR
tAEW
50%
50%
AE
ADDRESS
tAS
50%
50% 50%
50%
50%
D0-D3
SWITCH
ON
OFF
50%
tDS
tAH
tDH
50%
tPLH/tPHL
tPAE
tPLH/tPHL
tMR
tMRR
Figure 6 - Control Memory Timing Diagram
Memory
Reset
MR
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↓
0
0
↓
0
0
↓
0
0
↓
0
0
↓
0
0
↓
0
0
↓
0
NOTES:
Address
Enable
AE
Address
A2 A1 A0
Addressed
Line
Input Data To Control
Memory
D3
D2
D1
D0
X
X
X
X
ALL
X
X
X
X
0
X
X
X
NONE
X
X
X
X
1
0
0
0
L0
1
0
0
0
L0
1
0
0
0
L0
1
0
0
0
L0
1
0
0
0
L0
1
0
0
0
L0
1
0
0
0
L0
1
0
0
0
L0
1
0
0
0
L0
1
0
0
0
L0
1
0
0
0
L0
1
0
0
0
L0
1
0
0
0
L0
1
0
0
0
L0
1
0
0
0
L0
1
0
0
0
L0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
0
0
1
L1
↓
↓
↓
↓
↓
1
0
0
1
L1
0
0
0
0
↓
↓
↓
↓
1
1
1
1
1
0
1
0
L2
↓
↓
↓
↓
↓
1
0
1
0
L2
0
0
0
0
↓
↓
↓
↓
1
1
1
1
1
0
1
1
L3
↓
↓
↓
↓
↓
1
0
1
1
L3
0
0
0
0
↓
↓
↓
↓
1
1
1
1
1
1
0
0
L4
↓
↓
↓
↓
↓
1
1
0
0
L4
0
0
0
0
↓
↓
↓
↓
1
1
1
1
1
1
0
1
L5
↓
↓
↓
↓
↓
1
1
0
1
L5
0
0
0
0
↓
↓
↓
↓
1
1
1
1
1
1
1
0
L6
↓
↓
↓
↓
↓
1
1
1
0
L6
0
0
0
0
↓
↓
↓
↓
1
1
1
1
1
1
1
1
L7
↓
↓
↓
↓
↓
1
1
1
1
L7
0
0
0
0
↓
↓
↓
↓
1
1
1
1
Table 1 - Address Decode Truth Table
0 - Low Logic Level
1 - High Logic Level
X - Don’t Care Condition
+ - Indicates Connection Between Junctor and Addressed Line
• - Indicates No Connection Between Junctor and Addressed Line
Junctors Connected To
Addressed Line
J3
J2
J1
J0
All Switches "OFF"
No Change of State
•
•
•
•
•
•
•
+
•
•
+
•
•
•
+
+
•
+
•
•
•
+
•
+
•
+
+
•
•
+
+
+
+
•
•
•
+
•
•
+
+
•
+
•
+
•
+
+
+
+
•
•
+
+
•
+
+
+
+
•
+
+
+
+
•
•
•
•
↓
↓
↓
↓
+
+
+
+
•
•
•
•
↓
↓
↓
↓
+
+
+
+
•
•
•
•
↓
↓
↓
↓
+
+
+
+
•
•
•
•
↓
↓
↓
↓
+
+
+
+
•
•
•
•
↓
↓
↓
↓
+
+
+
+
•
•
•
•
↓
↓
↓
↓
+
+
+
+
•
•
•
•
↓
↓
↓
↓
+
+
+
+
3-8
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