IDT71V256SA View Datasheet(PDF) - Integrated Device Technology
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IDT71V256SA Datasheet PDF : 6 Pages
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IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2, 3, 4)
ADDRESS
t WC
t AW
CS
tAS
WE
DATAIN
tCW (5)
tWR
t DW
t DH
DATA VALID
3101 drw 10
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the spectified tWP.
ORDERING INFORMATION - COMMERCIAL
IDT71V256
SA
XX
Power Speed
X
Package
X
Process/
Temperature
Range
Blank Commercial (0°C to +70°C)
Y
300 mil SOJ (SO28-5)
TP
300 mil Plastic DIP (P28-2)
PZ
TSOP Type I (SO28-8)
10
12
15
Speed in nanoseconds
20
3101 drw 11
ORDERING INFORMATION - INDUSTRIAL
IDT71V256
SA
XX
Power Speed
X
Package
X
Process/
Temperature
Range
I
Industrial (-40°C to +85°C)
Y
300 mil SOJ (SO28-5)
PZ
TSOP Type I (SO28-8)
15
Speed in nanoseconds
3101 drw 12
6
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