VPC3230D View Datasheet(PDF) - Micronas

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VPC3230D

Comb Filter Video Processor

Micronas 

PRELIMINARY DATA SHEET

VPC 323xD

Comb Filter Video Processor

1. Introduction

The VPC 323xD is a high-quality, single-chip video

front-end, which is targeted for 4:3 and 16:9, 50/60-Hz

and 100/120 Hz TV sets. It can be combined with other

members of the DIGIT3000 IC family (such as

DDP 331x) and/or it can be used with 3rd-party prod-

ucts.

The main features of the VPC 323xD are

– high-performance adaptive 4H comb filter Y/C sepa-

rator with adjustable vertical peaking

– multi-standard color decoder PAL/NTSC/SECAM

including all substandards

– four CVBS, one S-VHS input, one CVBS output

– two RGB/YCrCb component inputs, one Fast Blank

(FB) input

– integrated high-quality A/D converters and associ-

ated clamp and AGC circuits

– multi-standard sync processing

– linear horizontal scaling (0.25 ... 4), as well as

non-linear horizontal scaling ‘Panoramavision’

– PAL+ preprocessing

– line-locked clock, data and sync, or 656-output

interface

– peaking, contrast, brightness, color saturation and

tint for RGB/ YCrCb and CVBS/S-VHS

– high-quality soft mixer controlled by Fast Blank

– P-31-6-IPofpnroocrmesaslinsgizefo)rwfoithur8p-bicitturreesosilzuetison(14--, 19--, 1--1--6--, or

– 15 predefined PIP display configurations and expert

mode (fully programmable)

– control interface for external field memory

– I2C-bus interface

– one 20.25-MHz crystal, few external components

– 80-pin PQFP package

1.1. System Architecture

Fig.1–1 shows the block diagram of the video proces-

sor

CIN

VIN1

VIN2

VIN3

VIN4

VOUT

RGB/

YCrCb

FB

RGB/

YCrCb

Analog

Front-end

AGC

2 × ADC

Adaptive

Comb

Filter

NTSC

PAL

Color Y

Decoder

NTSC Cr

PAL

SECAM

Cb

Saturation

Tint

Mixer

Y 2D Scaler

PIP

Cr Panorama

Mode

Cb Contrast

Brightness

Peaking

Output

Formatter

ITU-R 656

ITU-R 601

Memory

Control

Analog Y/G Processing Y

Component U/B

Front-End

Matrix

Contrast

Cr

V/R Saturation Cb

4 x ADC FB Brightness FB

Tint

I2C Bus

Clock

Gen.

Sync

+

Clock

Generation

Y OUT

CrCb

OUT

YCOE

FIFO

CNTL

LL Clock

H Sync

V Sync

AVO

Fig. 1–1: Block diagram of the VPC 323xD

20.25 MHz I2C Bus

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