HB7121B View Datasheet(PDF) - Hyundai Micro Electronics
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Description
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HB7121B Datasheet PDF : 29 Pages
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Electronics Industries Co., Ltd.
System IC Division
PRELIMINARY
INPUT / OUTPUT AC CHARACTERISTICS
HB7121B
CMOS IMAGE SENSOR
With 8-bit ADC
l All output timing delays are measured with output load 60[pF].
l Output delay include the internal clock path delay 6[ns] and output driving delay that changes in
respect to the output load, the operating environment, and a board design.
l Due to the variable valid time delay of the output, output signals may be latched in the negative
edge of MCLK for the stable data transfer between the image sensor and a host for less than
15MHz operation.
MCLK to HSYNC/VSYNC Timing
T1
MCLK
HSYNC/VSYNC
T1
T2
T1 : MCLK rising to HSYNC/VSYNC valid maximum time : 18ns [output load: 60pF]
T2 : HSYNC/VSYNC valid time : minimum 1clock(subject to T1, T2 timing rule)
MCLK to DATA Timing
T3
MCLK
DATA[7:0]
T3
valid data
T3 : MCLK rising to DATA valid maximum time : 18ns [output load: 60pF]
Note) HSYNC signal is high when valid data is on the DATA bus.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA21991011R_1.0
-4-
1999 Hyundai System IC Division
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