TA8030F View Datasheet(PDF) - Toshiba

Part Name

Description

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TA8030F

WATCHDOG TIMER

Toshiba 

TA8030S/F

FUNCTIONAL DESCRIPTION

About reset timer operation (See the timing chart)

The following explains the TA8030S/F's voltage monitoring and reset timer operations and how to use these

functions.

(1) Voltage monitoring function (1)

The power input VCC pin of this IC also serves as a voltage detection pin. When the VCC voltage exceeds

4.25V after the IC is powered on, the power-on reset timer starts operating from that point in time. When

the IC is powered off and VCC drops below 4.25V, TC starts discharging and a reset signal is output when

the voltage drops below 40% of VCC. Also, if VCC goes down for some reason during normal operation, a

reset signal is output in the same way as described above, and when VCC is up again and exceeds 4.25V, the

power-on reset timer starts operating from that point in time.

The reset signal is forwarded to the RST1 pin.

(2) Voltage monitoring function (2)

The RST2 pin outputs a high when the VCC voltage rises above 4.65V and outputs a low when it falls below

4.48V. This function only monitors the voltage operating independently of Voltage monitoring function (1)

and the reset timer function. Since when the voltage drops the RST2 output is inverted before a system

reset signal is output from RST1 , this function can be used to inhibit writing to memory.

μ Also, this voltage detection has 3 s of response delay, td2, to prevent a reset from being generated

inadvertently by minute noise. (For td2, refer to AC Electrical Characteristics.)

(3) Power-on reset timer function

The device is held in a reset state for a predetermined time until the 5V constant voltage stabilizes at

power-on and until the oscillating clock of the CPU, etc. stabilizes before being freed from the reset state.

This time can be set to any desired duration by using the appropriate resistor and capacitor values

connected external to the TC pin.

When the VCC voltage exceeds 4.25V, the system starts charging the capacitor and when this charging

voltage exceeds 2V, the reset signal is inverted to deactivate the reset.

(4) Watchdog timer function

The WD pin between the CPU system and this IC is connected with an differential circuit. This is to ensure

that when a failure occurs in the CPU system, a low signal is input to the WD pin no matter whether the

clock output has stopped in the high or the low state. When the WD pin is fixed high, the watchdog timer

stops operating.

If only the power-on reset timer is needed in your system, connect the WD pin to RST1 .

4

2002-02-27

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