Instruction Code
010100 trrrrrrr
110110 iiiiiiii
011111 trrrrrrr
010110 trrrrrrr
Mnemonic
Operands
XORWR R, t
XORWI i
COMR R, t
RRR R, t
Function
Exclu. OR W and register
Exclu. OR W and immediate
Complement register
Rotate right register
010101 trrrrrrr
RLR R, t
Rotate left register
010000 1xxxxxxx
010001 0rrrrrrr
0000bb brrrrrrr
0010bb brrrrrrr
0001bb brrrrrrr
0011bb brrrrrrr
1000nn nnnnnnnn
CLRW
CLRR R
BCR R, b
BSR R, b
BTSC R, b
BTSS R, b
LCALL n
Clear working register
Clear register
Bit clear
Bit set
Bit Test, skip if clear
Bit Test, skip if set
Long CALL subroutine
1010nn nnnnnnnn
110000 nnnnnnnn
LJUMP n
CALL n
Long JUMP to address
Call subroutine
110001 iiiiiiii
11001n nnnnnnnn
RTWI i
JUMP n
Return, place immediate to W
JUMP to address
MDT2030(CC)
Operating
R ⊕ W→t
i ⊕ W→W
/R→t
R(n) →R(n-1),
C→R(7), R(0)→C
R(n)→r(n+1),
C→R(0), R(7)→C
0→W
0→R
0→R(b)
1→R(b)
Skip if R(b)=0
Skip if R(b)=1
n→PC,
PC+1→Stack
n→PC
n→PC,
PC+1→Stack
Stack→PC,i→W
n→PC
Status
Z
Z
Z
C
C
Z
Z
None
None
None
None
None
None
None
None
None
Note :
W
WT
TMODE
CPIO
TF
PF
PC
OSC
Inclu.
Exclu.
AND
: Working register
: Watchdog timer
: TMODE mode register
: Control I/O port register
: Timer overflow flag
: Power loss flag
: Program Counter
: Oscillator
: Inclusive ‘∪’
: Exclusive ‘⊕’
: Logic AND ‘∩’
b:
t:
0
1
R:
C:
HC :
Z:
/:
x:
i:
n:
Bit position
Target
: Working register
: General register
General register address
Carry flag
Half carry
Zero flag
Complement
Don’t care
Immediate data ( 8 bits )
Immediate address
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 7
2005/6 Ver. 1.4