SI1141(2011) View Datasheet(PDF) - Silicon Laboratories
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SI1141 Datasheet PDF : 66 Pages
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Si1141/42/43
Figure 4. Typical Ambient Light Sense Performance Curves (Preliminary)
2.4. Host Interface
The host interface to the Si1141/42/43 consists of three pins:
SCL
SDA
INT
SCL and SDA are standard open-drain pins as required for I2C operation.
The Si1141/42/43 asserts the INT pin to interrupt the host processor. The INT pin is an open-drain output. A pull-up
resistor is needed for proper operation. As an open-drain output, it can be shared with other open-drain interrupt
sources in the system.
For proper operation, the Si1141/42/43 is expected to fully complete its Initialization Mode prior to any activity on
the I2C.
The INT, SCL, and SDA pins are designed so that it is possible for the Si1141/42/43 to enter the Off Mode by
software command without interfering with normal operation of other I2C devices on the bus.
The Si1141/42/43 I2C slave address is 0x5A. The Si1141/42/43 also responds to the global address (0x00) and the
global reset command (0x06). Only 7-bit I2C addressing is supported; 10-bit I2C addressing is not supported.
Conceptually, the I2C interface allows access to the Si1141/42/43 internal registers. Table 15 on page 25 is a
summary of these registers.
An I2C write access always begins with a start (or restart) condition. The first byte after the start condition is the I2C
address and a read-write bit. The second byte specifies the starting address of the Si1141/42/43 internal register.
Subsequent bytes are written to the Si1141/42/43 internal register sequentially until a stop condition is
encountered. An I2C write access with only two bytes is typically used to set up the Si1141/42/43 internal address
in preparation for an I2C read.
The I2C read access, like the I2C write access, begins with a start or restart condition. In an I2C read, the I2C
Preliminary Rev. 0.5
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