74HC160 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

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74HC160

Presettable synchronous BCD decade counter; asynchronous reset

NXP Semiconductors. 

Nexperia

74HC160

Presettable synchronous BCD decade counter; asynchronous reset

9,

3(LQSXW

*1'

9,

&3LQSXW

*1'

9,

'QLQSXW

*1'

90

WVX

WK

90

WVX

WK

90

WVX

WK

WVX

WK

DDD

The shaded areas indicate when the input is permitted to change for predictable output performance.

Measurement points are given in Table 8.

Fig 12. The data input (Dn) and parallel enable input (PE) set-up and hold times

9,

&(3&(7

LQSXW

*1'

9,

&3LQSXW

*1'

90

WVX

WK

90

WVX

WK

DDD

The shaded areas indicate when the input is permitted to change for predictable output performance.

Measurement points are given in Table 8.

Fig 13. The count enable input (CEP) and count enable carry input (CET) set-up and hold times

Table 8. Measurement points

Input

VM

0.5  VCC

VI

GND to VCC

Output

VM

0.5  VCC

74HC160

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 27 September 2016

© Nexperia B.V. 2017. All rights reserved

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