74HC160(2019) View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
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74HC160 Datasheet PDF : 15 Pages
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Nexperia
74HC160
Presettable synchronous BCD decade counter; asynchronous reset
5.2. Pin description
Table 2. Pin description
Symbol
MR
CP
D0, D1, D2, D3
CEP
GND
PE
CET
Q0, Q1, Q2, Q3
TC
VCC
Pin
1
2
3, 4, 5, 6
7
8
9
10
14, 13, 12, 11
15
16
Description
asynchronous master reset (active LOW)
clock input (LOW-to-HIGH, edge triggered)
data input
count enable input
ground (0 V)
parallel enable input (active LOW)
count enable carry input
flip-flop output
terminal count output
supply voltage
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
qn = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition.
Operating mode
Inputs
Outputs
MR
CP
CEP CET PE
Dn
Qn
TC
Reset (clear)
L
X
X
X
X
X
L
L
Parallel load
H
↑
X
X
I
I
L
L
H
↑
X
X
I
h
H
[1]
Count
H
↑
h
h
h
X
count [1]
Hold (do nothing)
H
X
I
X
h
X
qn
[1]
H
X
X
I
h
X
qn
L
[1] The TC output is HIGH when CET is HIGH and the counter is at terminal count (HLLH);
0
1
2
3
4
15
5
14
6
13
7
Fig. 6. State diagram
12
11
10
9
8
aaa-024742
74HC160
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 27 March 2019
© Nexperia B.V. 2019. All rights reserved
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