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SCY99079ADR2G View Datasheet(PDF) - ON Semiconductor

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SCY99079ADR2G Datasheet PDF : 28 Pages
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VCC
VFB
IpFlag
Timer
Can be very
slow...
DAP018A/B/C/D/F
regulation
VCClatch
VCCreset
Duration given
by aux. cap.
Current loop
action keeps FB
OK (CC operation)
VCC(on)
VCC(min)
Drv
< 100ms
< 100ms
Figure 35. First Fault Mode Case
First fault mode case, the auxiliary winding collapses but feedback is still there (0.22 mF timer capacitor)
2. In the second case, the converter operates in
regulation, but the output is severely overloaded.
However, due to the bad coupling between the
power and the auxiliary windings, the controller
VCC does not go low. The peak current is pushed
to the maximum and the timer starts to count.
Upon completion, all pulses are stopped and
dualstartup hiccup mode is entered. If the fault
goes away, the SMPS resumes operation.
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