CYIL2SM1300-EVAL View Datasheet(PDF) - ON Semiconductor
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CYIL2SM1300-EVAL Datasheet PDF : 41 Pages
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CYIL2SM1300AA
Table 13. Internal Registers (continued)
Block
LVDS clk
divider
Register Name Address [6..0]
lvdsmain
5
lvdspwd1
6
lvdspwd2
7
Fix6
8
AFE
afebias
9
afemode
10
afepwd1
11
afepwd2
12
Bias block
bandgap
13
Image Core imcmodes
14
Fix7
15
Fix8
16
imcbias1
17
imcbias2
18
imcbias3
19
Imcbias4
20
Field
[3:0]
[7:4]
[7:0]
[5:0]
[6]
[7]
[7:0]
[3:0]
[2:0]
[5:3]
[6]
[7:0]
[3:0]
[0]
[1]
[2]
[5:3]
[0]
[1]
[2]
[3]
[4]
[5]
[7:0]
[7:0]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
Reset Value
Description
‘0110’
lvds trim
0
clkadc phase
0x00
Power down channel 7:0
0
Power down channel 13:8
0
Power down all channels
0
lvds test mode
0x00
Reserved, fixed value
‘1000’
afe current biasing
‘111’
vrefp, vrefm settings
‘000’
Pga settings
0
Power down AFE
0x00
Power down adc_channel_2x 7 to 0
0x00
Power down adc_channel_2x 11 to 8
‘0’
Power down bandgap and currents
‘1’
External resistor
‘0’
External voltage reference
‘000’
Bandgap trimming
0
Power down
‘1’
Enable vrefcol regulator
‘1’
Enable precharge regulator
0
Disable internal bias for vprech
‘1’
Disable column load
‘0’
clkmain invert
0x00
Reserved, fixed value
0x00
Reserved, fixed value
‘1000’
Bias colfpn DAC buffer
‘1000’
Bias precharge regulator
‘1000’
Bias pixel precharge level
‘1000’
Bias column ota
‘1000’
Bias column unip fast
‘1000’
Bias column unip slow
‘1000’
Bias column load
‘1000’
Bias column precharge
Document Number: 001-24599 Rev. *C
Page 11 of 41
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