CM8064401831400S View Datasheet(PDF) - Intel

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CM8064401831400S

Intel® Xeon® Processor E5-1600, E5-2600, and E5-4600 v3 Product Families, Volume 1 of 2, Electrical

Intel 

Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Introduction

1.1.3

Document

• Volume 3B: System Programming Guide

Intel® 64 and IA-32 Architectures Optimization Reference Manual

Intel® Virtualization Technology Specification for Directed I/O

Architecture Specification

Intel® Trusted Execution Technology Software Development Guide

Document Number/Location

http://www.intel.com/

content/www/us/en/intelligent-

systems/intel-technology/vt-

directed-io-spec.html

http://www.intel.com/technology/

security/

Terminology

ASPM

BMC

Cbo

Term

DDR4

DMA

DMI2

DSB

DTLB

DTS

ECC

Enhanced Intel SpeedStep®

Technology

Execute Disable Bit

FLIT

Functional Operation

GSSE

HA

ICU

IFU

Description

Active State Power Management

Baseboard Management Controller

Caching Agent (also referred to as CA). It is a term used for the

internal logic providing ring interface to LLC and Core. The Cbo is a

functional unit in the processor. A Caching Agent is defined per the

RS - Intel® QuickPath Interconnect External Link Specification.

Fourth generation Double Data Rate SDRAM memory technology.

Direct Memory Access

Direct Media Interface Gen2 operating at PCI Express 2.0 speed.

Data Stream Buffer. Part of the processor core architecture.

Data Translation Look-aside Buffer. Part of the processor core

architecture.

Digital Thermal Sensor

Error Correction Code

Allows the operating system to reduce power consumption when

performance is not needed.

The Execute Disable bit allows memory to be marked as executable

or non-executable, when combined with a supporting operating

system. If code attempts to run in non-executable memory the

processor raises an error to the operating system. This feature can

prevent some classes of viruses or worms that exploit buffer

overrun vulnerabilities and can thus help improve the overall

security of the system. See the Intel® 64 and IA-32 Architectures

Software Developer's Manuals for more detailed information.

Flow Control Unit. The Intel QPI Link layer's unit of transfer; 1 Flit =

80-bits.

Refers to the normal operating conditions in which all processor

specifications, including DC, system bus, signal quality, mechanical,

and thermal, are satisfied.

Extension of the SSE/SSE2 (Streaming SIMD Extensions) floating

point instruction set to 256b operands.

A Home Agent (HA) orders read and write requests to a piece of

coherent memory.

Instruction Cache Unit. Part of the processor core architecture.

Instruction Fetch Unit. Part of the processor core.

continued...

Intel® Xeon® Processor E5-1600, E5-2600, and E5-4600 v3 Product Families, Volume 1 of 2, Electrical

Datasheet

10

June 2015

Order No.: 330783-002

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