RS5C372B-E2(1997) View Datasheet(PDF) - RICOH Co.,Ltd.
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RS5C372B-E2 Datasheet PDF : 39 Pages
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RS5C372B
transmission. When the master is the receiver, it generates no acknowledge signal after the last 1 byte of data
from the slave to tell the transmitter that data transmission has completed when the slave side (transmitter)
continues to release the SDA pin so that the master will be able to generate Stop Condition.
SCL
from master
1
2
SDA
from transmitter
SDA
from reciever
Start
Condition
8
9
Acknowledge
signal
1.2.3. Data transmission format in I2C-bus
I2C-bus generates no CE signals. In place of it each device has a 7bit slave address allocated. The first 1byte
is allocated to this 7bit of slave address and to the command (R/W) for which data transmission direction is
designated by the data transmission thereafter. 7bit address is sequentially transmitted from the MSB and 2
and after bytes are read, when 8bit is “H” and write when “L”.
The slave address of the RS5C372B is specified at (0110010).
At the end of data transmission/receiving stop condition is generated to complete transmission. However, if
start condition is generated without generating Stop Condition, Repeated Start Condition is met and
transmission/receiving data may be continued by setting the slave address again. Use this procedures when
the transmission direction needs to be changed during one transmission.
Data is written into the slave S
from the master
Slave Address 0 A
Data
A
Data
AP
(0110010)
R/W=0(Write)
When data is read from the S
slave immediately after 7bit
addressing from the master
Slave Address 1 A
Data
A
Data
/A P
(0110010)
R/W=1(Read)
Inform read has been completed by not generating
an acknowledge signal, to the slave side.
When the transmission S
direction is to be changed
during transmission.
Slave Address 0 A
Data
(0110010)
R/W=0(Write)
A Sr Slave Address 1
(0110010) R/W=1(Read)
A
Data
A
Data
/A P
from master to slave
S Start Condition
Inform read has been completed by not generating
an acknowledge signal, to the slave side.
from slave to master
A A /A Acknowledge
P Stop Condition
Sr Repeated Start Condition
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