RS5C372B(1997) View Datasheet(PDF) - RICOH Co.,Ltd.
Part Name
Description
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RS5C372B Datasheet PDF : 39 Pages
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RS5C372B
Pulse mode
CTFG bit
/INTR pin
Approx. 92µs (32.768KHz crystal is used)
Approx. 94µs (32.000KHz cristal is used)
(Counting up of seconds)
*) Since counting up of seconds and the falling edge has a time lag of approx. 92µs (at
32.768kHz) (approx. 94µs when 32.000kHz crystal is used), time with apparently
approx. one second of delay from time of the real-time clock may be read when time is
read in synchronization with the falling edge of output.
Level mode
CTFG bit
/INTR pin
Write 0 to CTFG bit
Write 0 to CTFG bit
(second count-up) (second count-up) (second count-up)
2.2. Control Register 2 ( Internal address at Fh )
D7
D6
D5
D4
D3
D2
D1
D0
-
-
/12⋅24 ADJ /CLEN CTFG AAFG BAFG (For Write operation )
0
0
/12⋅24 XSTP /CLEN CTFG AAFG BAFG (For Read operation )
0
0
unde-
1
0
0
0
0 Default (*)
fined
*)The default means read values when XSTP=”1” by after initial power-on or supply voltage drop,etc.
2.2.1. /12⋅24
/12⋅24-hour Time Display Selection bit
/12⋅24
Description
0
12-hour time display system
1
24-hour time display system
Being set this bit at “0” indicates 12-hour display system while “1” indicates 24-hour system.
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