627 698¡@BAC 82D7E8'F9DA9D8¡@969AC G9@BC 8G
H¤I¦P I¨QR S R¦P
T¤U¦QV W"X`Ya b
Output Voltage (10kΩ // 10 pF)
Output Voltage (10kΩ // 10 pF)
Coarse CDAC (5 Bit)
Fine CDAC (7 Bit)
Startup Time
Vout1
Vout2
CCSTEP
CFSTEP
TSTART
iqprpts¡urvxw'y2 ¡s9vBu92v
The offset adjustment is achieved with two steps,
first the coarse register is adjusted while the fine
tuning register is set to middle position. After that
the fine tuning register is used for the final
adjustment.
DA1173.001
May 27, 1999
c¦U¤d
1.0
1.0
135
12
Y¡I e
10
f b¦a Shg"W¨S R
Vpp
Vpp
fF
fF
ms
The I2C bus is organized so that only one address
is used for the coarse and fine tuning. After the
address the seven bit fine tuning is written followed
by the five bit coarse register. Always eight bits are
written according to I2C standard. The seven and
five bits are filled with zeros in front (the MSB
place).
3