IDT7024S15PF View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

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IDT7024S15PF

HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7024S/L

HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE IV —

ADDRESS BUSY ARBITRATION

Inputs

Outputs

A0L-A11L

CEL CER A0R-A11R BUSYL(1) BUSYR(1)

Function

X

X NO MATCH

H

H

Normal

H

X

MATCH

H

H

Normal

X

H

MATCH

H

L

L

MATCH

(2)

H

Normal

(2)

Write Inhibit(3)

NOTES:

2740 tbl 16

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the

IDT7024 are push pull, not open drain outputs. On slaves, the BUSY asserted input internally inhibits write.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable

after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs cannot be low

simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are

internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.

TRUTH TABLE V — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1,2)

Functions

D0 - D15 Left D0 - D15 Right

Status

No Action

1

1

Semaphore free

Left Port Writes "0" to Semaphore

0

1

Left port has semaphore token

Right Port Writes "0" to Semaphore

0

1

No change. Right side has no write access to semaphore

Left Port Writes "1" to Semaphore

1

0

Right port obtains semaphore token

Left Port Writes "0" to Semaphore

1

0

No change. Left port has no write access to semaphore

Right Port Writes "1" to Semaphore

0

1

Left port obtains semaphore token

Left Port Writes "1" to Semaphore

1

1

Semaphore free

Right Port Writes "0" to Semaphore

1

0

Right port has semaphore token

Right Port Writes "1" to Semaphore

1

1

Semaphore free

Left Port Writes "0" to Semaphore

0

1

Left port has semaphore token

Left Port Writes "1" to Semaphore

1

1

Semaphore free

NOTES:

2740 tbl 19

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7024.

2. There are eight semaphore flags written to via I/O0 and read from all the I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.

FUNCTIONAL DESCRIPTION

The IDT7024 provides two ports with separate control,

address and I/O pins that permit independent access for reads

or writes to any location in memory. The IDT7024 has an

automatic power down feature controlled by CE. The CE

controls on-chip power down circuitry that permits the

respective port to go into a standby mode when not selected

(CE High). When a port is enabled, access to the entire

memory location FFF (HEX) and to clear the interrupt flag

(INTR), the right port must access the memory location FFF.

The message (16 bits) at FFE or FFF is user-defined, since it

is an addressable SRAM location. If the interrupt function is

not used, address locations FFE and FFF are not used as mail

boxes, but as part of the random access memory. Refer to

Truth Table for the interrupt operation.

memory array is permitted.

BUSY LOGIC

INTERRUPTS

Busy Logic provides a hardware indication that both ports

If the user chooses to use the interrupt function, a memory

location (mail box or message center) is assigned to each port.

The left port interrupt flag (INTL) is asserted when the right port

writes to memory location FFE (HEX), where a write is defined

as the CE = R/W = VIL per the Truth Table. The left port clears

the interrupt by access address location FFE access when

CER = OER = VIL, R/W is a "don't care". Likewise, the right port

interrupt flag (INTR) is asserted when the left port writes to

of the RAM have accessed the same location at the same

time. It also allows one of the two accesses to proceed and

signals the other side that the RAM is “Busy”. The busy pin can

then be used to stall the access until the operation on the other

side is completed. If a write operation has been attempted

from the side that receives a busy indication, the write signal

is gated internally to prevent the write from proceeding.

The use of busy logic is not required or desirable for all

6.15

16

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