CDP1853C3 View Datasheet(PDF) - Intersil
Part Name
Description
View to exact match
CDP1853C3 Datasheet PDF : 7 Pages
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CDP1853/3, CDP1853C/3
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD)
(All Voltages Referenced to VSS Terminal)
CDP1853/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1853C/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . ±10mA
Thermal Information
Thermal Resistance (Typical)
θJA (oC/W) θJC (oC/W)
SBDIP Package . . . . . . . . . . . . . . . . . .
85
22
Device Dissipation Per Output Transistor
TA = Full Package Temperature Range
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature
Package Type D. . . .
Range
......
(TA)
....
.
.
.
.
.
.
.
.
.
.
.
.-55oC
to
+125oC
Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ±1/32 In. (1.59 ± 0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
Timing Diagrams
N0 - N2
OUTPUT 0 - 7
TN0
FIGURE 2A. N - INPUTS TO OUTPUTS DELAY TIME
CE
OUTPUT 0 - 7
TEOH
TEOL
FIGURE 2B. CE TO OUTPUT DELAY TIME
MIN. CLOCK B
PULSE WIDTH
CLOCK B
TCBCB
MIN. CLOCK A
PULSE WIDTH
CLOCK A
OUTPUT 0 - 7
TCACA
TAO
OUTPUT 0 - 7
TBO
FIGURE 2C. CLOCK B TO OUTPUT DELAY TIME
NOTE:
(SEE NOTE 1)
1. To measure TAO, Clock B must be tied low.
FIGURE 2D. CLOCK A TO OUTPUT DELAY TIME
FIGURE 2. PROPAGATION DELAY TIME DIAGRAMS
TPA
TPB
CE
EN
(NOTE 1)
OUTPUT
NOTE:
1. Output enabled when EN = high. Internal signal shown for refer-
ence only (see Figure 1).
FIGURE 3. TIMING DIAGRAM
A
B
C
CHIP ENABLE
VDD
OUT 0
N0
OUT 1
N1
OUT 2
N2
OUT 3
CE OUT 4
CLK B OUT 5
CLK A OUT 6
OUT 7
FIGURE 4. N-BIT DECODER USED AS A 1 OF 8 DECODER
4-44
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