Bt8110/8110B
High-Capacity ADPCM Processor
2.0 Functional Description
2.4 Hardware Control
2.4 Hardware Control
Some applications require precise timing of the modification of the code selected,
transparent operation, or coding law. In these cases, the control signals can be
provided by hardware and are updated each time a PCM encoder input or an
ADPCM decoder input is applied. Serial or parallel inputs can be used. Table 2-4.
defines the functions and inputs of the control pins for hardware control.
Table 2-4. Bt8110/8110B Connection for Hardware Mode
Bt8110/8110B
Pin
Function
Hardware Mode
Pin #
MICREN
µP Enable
GND
23
ALE
Optional Coding
OPT (CODE[3])
29
WR*
Enable A-Law PCM
A-LAW
3
CS
Enable Transparent
TRNSPT
22
AD[0]
Mode Bit 0
MODE[0]
11
AD[1]
Mode Bit 1
MODE[1]
12
AD[2]
Mode Bit 2
MODE[2]
13
AD[3]
32-Channel Operation
CH32
19
AD[4]
Code Bit 0
CODE[0]
24
AD[5]
Code Bit 1
CODE[1]
25
AD[6]
Embedded Coding
EMB (CODE[2])
28
NOTE(S): The four CODE[n] pins (24, 25, 28, and 29) address the 14 ROM code locations
when using hardware control mode.
100060C
Conexant
2-13