LSH32JC20 View Datasheet(PDF) - LOGIC Devices Incorporated
Part Name
Description
View to exact match
LSH32JC20 Datasheet PDF : 9 Pages
| |||
DEVICES INCORPORATED
LSH32
32-bit Cascadable Barrel Shifter
TABLE 1. WRAP MODE SHIFT CODE DEFINITIONS
significant bit of a 6-bit two’s comple-
ment shift code, comprised of R/L
Shift Code Y31 Y30 Y29 ••• Y16 Y15 ••• Y2 Y1 Y0 concatenated with the SI4–SI0 lines.
00000
Thus a positive shift code (R/L = 0)
I31 I30 I29 ••• I16 I15 ••• I2 I1 I0 results in a left shift of 0–31 positions,
00001
I30 I29 I28 ••• I15 I14 ••• I1 I0 I31 and a negative code (R/L = 1) a right
00010
00011
•
•
I29 I28 I27 ••• I14 I13 ••• I0 I31 I30 shift of up to 32 positions. The LSH32
I28 I27 I26 ••• I13 I12 ••• I31 I30 I29 can thus effectively select any contigu-
ous 32-bit field out of a (sign extended
•
•
• ••• •
• ••• •
•
•
and zero filled) 96-bit "input."
•
•
• ••• •
• ••• •
•
•
•
01111
10000
10001
10010
•
•
•
•
•
• ••• •
• ••• •
•
• OUTPUT MULTIPLEXER
I16 I15 I14 ••• I1
I0 ••• I19 I18 I17 The shift array outputs are applied to
I15 I14 I13 ••• I0 I31 ••• I18 I17 I16 a 2:1 multiplexer controlled by the
I14 I13 I12 ••• I31 I30 ••• I17 I16 I15 MS/LS select line. This multiplexer
I13 I12 I11 ••• I30 I29 ••• I16 I15 I14 makes available at the output pins
•
•
• ••• •
• ••• •
•
• either the most significant or least
•
•
• ••• •
• ••• •
•
• significant 16 outputs of the shift
array.
•
•
• ••• •
• ••• •
•
•
11100
I3 I2 I1 ••• I20 I19 ••• I6 I5 I4 PRIORITY ENCODER
11101
11110
I2 I1 I0 ••• I19 I18 ••• I5 I4 I3
The 32-bit input bus drives a priority
I1 I0 I31 ••• I18 I17 ••• I4 I3 I2 encoder which is used to determine
11111
I0 I31 I30 ••• I17 I16 ••• I3 I2 I1 the first significant position for
purposes of normalization. The
TABLE 2. FILL MODE SHIFT CODE DEFINITIONS — LEFT SHIFT
priority encoder produces a five-bit
code representing the location of the
Shift Code Y31 Y30 Y29 ••• Y16 Y15 ••• Y2 Y1 Y0 first non-zero bit in the input word.
Code assignment is such that the
00000
I31 I30 I29 ••• I16 I15 ••• I2 I1 I0 priority encoder output represents the
00001
I30 I29 I28 ••• I15 I14 ••• I1 I0 0 number of shift positions required to
00010
00011
•
I29 I28 I27 ••• I14 I13 ••• I0
0
0
left align the first non-zero bit of the
input word. Prior to the priority
I28 I27 I26 ••• I13 I12 ••• 0
0
0
encoder, the input bits are individu-
•
•
• ••• •
• ••• •
•
• ally exclusive OR’ed with the SIGN
•
•
•
• ••• •
• ••• •
•
• input. This allows normalization in
•
01111
10000
10001
•
•
• ••• •
• ••• •
•
• floating point systems using two’s
I16 I15 I14 ••• I1
I0 ••• 0
0
0
complement mantissa representation.
A negative value in two’s complement
I15 I14 I13 ••• I0
0 ••• 0
0
0
representation will cause the exclusive
I14 I13 I12 ••• 0 0 ••• 0 0 0 OR gates to invert the input data to
10010
I13 I12 I11 ••• 0 0 ••• 0 0 0 the encoder. As a result the leading
•
•
•
• ••• •
• ••• •
•
• significant digit will always be "1."
•
•
11100
•
•
• ••• •
• ••• •
•
• This affects only the encoder inputs;
the shift array always operates on the
•
•
• ••• •
• ••• •
•
• raw input data. The priority encoder
I3 I2 I1 ••• 0 0 ••• 0 0 0 function table is shown in Table 4.
11101
I2 I1 I0 ••• 0 0 ••• 0 0 0
11110
I1 I0 0 ••• 0 0 ••• 0 0 0
11111
I0 0 0 ••• 0 0 ••• 0 0 0
Special Arithmetic Functions
ffs2
08/16/2000–LDS.32-Q
Share Link: 