VP5511B View Datasheet(PDF) - Mitel Networks
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VP5511B Datasheet PDF : 19 Pages
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Video Blanking
The VP5311/VP5511 automatically performs standard
composite video blanking. Lines 1-9, 264-272 inclusive, as
well as the last half of line 263 are blanked in NTSC mode. In
PAL mode, lines 1-5, 311-318, 624-625 inclusive, as well as
the last half of line 623 are blanked.
The V bit within REC656 defines the video blanking when
TRSEL (bit 0 of GPSCTL register) is set low. When in
MASTER mode with TRSEL set high the video encoder is still
enabled. Therefore if these lines are required to be blank they
must have no video signal input.
Interpolator
The luminance and chrominance data are separately
passed through interpolating filters to produce output
sampling rates double that of the incoming pixel rate. This
reduces the sinx/x distortion that is inherent in the digital to
analog converters and also simplifies the analog
reconstruction filter requirements.
Digital to Analog Converters
The VP5311/VP5511 contained three 9 bit digital to
analog converters which produce the analog video signals.
The DACs use a current steering architecture in which bit
currents are routed to one of two outputs; thus the DAC has
true and complementary outputs. The use of identical current
sources and current steering their outputs means that
monotonicity is guaranteed. An on-chip voltage reference of
1.050V provides the necessary biasing. However, the
VP5311/VP5511 may be used in applications where an
external 1V reference is provided on the VREF pin, to adjust
the video levels. In this case, the external reference should be
temperature compensated and provide a low impedance
output.
The full-scale output currents of the DACs is set by an
external 769Ω resistor between the DACGAIN and GND pins.
An on-chip loop amplifier stabilises the full-scale output
current against temperature and power supply variations.
The analog outputs of the VP5311/VP5511 are capable of
directly driving doubly terminated 75Ω load then the
DACGAIN resistor is simply doubled.
Luminance, Chrominance and Composite Video Outputs
The Luminance video output (LUMAOUT pin 54) drives a
37.5Ω load at 1.0V, sync tip to peak white. It contains only the
luminance content of the image plus the composite sync
pulses. In the NTSC mode, a set-up level offset can be added
during the active video portion of the raster.
The Chrominance video output (CHROMAOUT pin 58)
drives a 37.5Ω load at levels proportional in amplitude to the
luma output (40 IRE pk-pk burst). This output has a fixed offset
current which will produce approximately a 0.5V DC bias
across the 37.5Ω load. Burst is injected with the appropriate
timing relative to the luma signal.
The composite video output (COMPOUT pin 56) will also
drive a 37.5Ω load at 1.0V, sync tip to peak white. It contains
both the luminance and chrominance content of the signal
plus the composite sync pulses.
The CVBS DAC output clipping feature limits the digital
data going into the DAC so that if it goes outside the range it
is limited to the maximum or minimum (511 or 000). This
feature is permanently enabled.
CVBSCLP in register GCR. When set to a '1' this bit
VP5311B/VP5511B
enables an envelope prediction circuit that establishes if the
chroma and luma added together is likely to go outside the
CVBS DAC limits. If it is, then a smooth rounding of the
chroma peaks is made to stop this happening. This prevents
any high frequency components being produced as with the
clipping function which will produce flat peaks. In practice
there will be some loss of saturation in the colour.
Output sinx/x compensation filters are required on all
video output, as shown in the typical application diagram, see
figs. 8 & 9.
Video Timing - Slave sync mode
The VP5311/VP5511 has an internal timing generator
which produces video timing signals appropriate to the mode
of operation. In the default (power up) slave mode, all timing
signals are derived from the input clock, PXCK, which must be
derived from a crystal controlled oscillator. Input pixel data is
latched on the rising edge of the PXCK clock.
The video timing generator produces the internal blanking
and burst gate pulses, together with the composite sync
output signal, using timing data (TRS codes) from the
Ancillary data stream in the REC656 input signal, (when
TRSEL (bit 0 of GPSCTL register) is set low).
HCNT
To ensure that the incoming data is sampled correctly a 10
bit binary number (HCNT) has to be programmed into the
SLAVE1 and 2 registers. This will allow the device's internal
horizontal counter to align with the video data, each bit
represents one 13.5MHz cycle. To calculate this use the
formula below:
NTSC
HCNT = SN + 119 (SN = 0 - 738)
HCNT = SN + 739 (SN = 739 - 857)
PAL
HCNT = SN + 127 (SN = 0 - 738)
HCNT = SN + 737 (SN = 737 - 863)
where SN is Rec. 656/601 sample number on which the
negative edge of HSYNC occurs.
SL_HS
A further adjustment is also required to ensure that the
correct Cr and Cb sample alignment. The bits SL_HS1-0
allows for four sampling positions in the CbYCrY sequence,
failure to set this correctly will mean corruption of the colour or
colour being interpreted as luma.
F_SWAP
If the field synchronisation is wrong it can be swapped by
setting this bit.
V_SYNC
When set to a '1' this bit allows an odd/even square wave
to provide the field synchronisation.
Example
NTSC
HSYNC occurs on Rec656 sample 721 (end of active
video), then;
HCNT = 721 + 119 = 839 = 348 Hex
SL_HS = 10 (for correct sample)
to set slave mode send .04w08pzfbw48pzffw01
9
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