NT68F62 View Datasheet(PDF) - Unspecified
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NT68F62 Datasheet PDF : 57 Pages
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NT68F62
System Registers (continued)
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Control Register for Polling (Read) Interrupt Groups & Clearing (Write) INTE0 & INTMUTE Interrupt Requests
$0016 NMIPOLL 00H
―
―
―
―
―
―
INTE0 INTMUTE R
―
―
―
―
―
―
CLRE0 CLRMUTE W
$0017 IRQPOLL 00H
―
―
―
―
―
IRQ2
IRQ1
IRQ0
R
Control Registers of Interrupt Enable
$0018
IENMI
00H
―
―
―
―
―
―
INTE0 INTMUTE RW
$0019
IEIRQ0
00H
―
―
INTS0
INTA0
INTTX0 INTRX0 INTNAK0 INTSTOP0 RW
$001A
IEIRQ1
00H
―
―
INTS1
INTA1
INTTX1 INTRX1 INTNAK1 INTSTOP1 RW
$001B
IEIRQ2
00H
―
―
―
―
INTADC
INTV
INTE1
INTMR
RW
Control Registers for Polling (Read) & Clearing (Write) Interrupt Requests
$001C
IRQ0
00H
―
―
INTS0
INTA0
INTTX0 INTRX0 INTNAK0 INTSTOP0 R
―
―
CLRS0 CLRA0 CLRTX0 CLRRX0 CLRNAK0 CLRSTOP0 W
$001D
IRQ1
00H
―
―
INTS1
INTA1
INTTX1 INTRX1 INTNAK1 INTSTOP1 R
―
―
CLRS1 CLRA1 CLRTX1 CLRRX1 CLRNAK1 CLRSTOP1 W
$001E
IRQ2
00H
―
―
―
―
INTADC
INTV
INTE1
INTMR
R
―
―
―
―
CLRADC CLRV
CLRE1
CLRMR
W
Selection of Edge Triggered for INTV, INTE0 & 1 Interrupts
$001F TRIGGER FFH
―
―
―
―
―
INTVR
INTE1R INTE0R R/W
Control Registers for Clearing Watch Dog Timer
$0020 CLR WDT
―
0
1
0
1
0
1
0
1
W
Control Register for DDC1/2B+ of Channel 0
$0021 CH0ADDR A0H ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
―
W
$0022 CH0TXDAT 00H
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
W
$0023 CH0RXDAT 00H
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
R
$0024
CH0CON
E0H ENDDC
MD1/ 2
―
START
STOP
―
TXACK
―
W
―
―
SRW
START
STOP
―
―
―
R
$0025
CH0CLK
FFH MODE
MRW RSTART
―
―
DDC2BR2 DDC2BR1 DDC2BR0 W
Control Register for DDC1/2B+ of Channel 1
$0026 CH1ADDR A0H ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
―
W
$0027 CH1TXDAT 00H
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
W
$0028 CH1RXDAT 00H
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
R
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