IS61SP6464 View Datasheet(PDF) - Integrated Silicon Solution

Part Name

Description

View to exact match

IS61SP6464

64K x 64 SYNCHRONOUS PIPELINE STATIC RAM

Integrated Silicon Solution 

IS61SP6464

READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

Symbol Parameter

-133 MHz

Min. Max.

tKC

Cycle Time

7.5 —

tKH

Clock High Time

3

—

tKL

Clock Low Time

3

—

tKQ

Clock Access Time

—

5

tKQX(1) Clock High to Output Invalid

1.5 —

tKQLZ(1,2) Clock High to Output Low-Z

0

—

tKQHZ(1,2) Clock High to Output High-Z

2

5

tOEQ

Output Enable to Output Valid

—

5

tOEQX(1) Output Disable to Output Invalid

0

—

tOELZ(1,2) Output Enable to Output Low-Z

0

—

tOEHZ(1,2) Output Disable to Output High-Z

—

—

tAS

Address Setup Time

2.5 —

tSS

Address Status Setup Time

2.5 —

tWS

Write Setup Time

2.5 —

tCES

Chip Enable Setup Time

2.5 —

tAVS

Address Advance Setup Time

2.5 —

tAH

Address Hold Time

0.5 —

tSH

Address Status Hold Time

0.5 —

tWH

Write Hold Time

0.5 —

tCEH

Chip Enable Hold Time

0.5 —

tAVH

Address Advance Hold Time

0.5 —

Notes:

1. Guaranteed but not 100% tested. This parameter is periodically sampled.

2. Tested with load in Figure 2.

-117 MHz

Min. Max.

8.5 —

3.4 —

3.4 —

—

5

1.5 —

0

—

2

5

—

5

0

—

0

—

—

—

2.5 —

2.5 —

2.5 —

2.5 —

2.5 —

0.5 —

0.5 —

0.5 —

0.5 —

0.5 —

ISSI ®

-100 MHz

Min. Max. Unit

10

—

ns

4

—

ns

4

—

ns

—

5

ns

2.5 —

ns

0

—

ns

2

5

ns

—

5

ns

0

—

ns

0

—

ns

2

5

ns

2.5 —

ns

2.5 —

ns

2.5 —

ns

2.5 —

ns

2.5 —

ns

0.5 —

ns

0.5 —

ns

0.5 —

ns

0.5 —

ns

0.5 —

ns

Integrated Silicon Solution, Inc. — 1-800-379-4774

9

Rev. A

04/17/01

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