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SST89C54-33-C-PJ View Datasheet(PDF) - Silicon Storage Technology

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Description
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SST89C54-33-C-PJ
SST
Silicon Storage Technology SST
SST89C54-33-C-PJ Datasheet PDF : 50 Pages
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FlashFlex51 MCU
SST89C54 / SST89C58
Preliminary Specifications
PIN DESCRIPTIONS (CONTINUED)
Symbol
Type1
Name and Functions
PSEN#
O/I
Program Store Enable: PSEN# is the Read strobe to External Program
1
Memory. When the SST89C54/58 are executing from Internal Program
Memory, PSEN# is inactive (high). When the device is executing code from
External Program Memory, PSEN# is activated twice each machine cycle,
except that two PSEN# activations are skipped during each access to External
2
Data Memory. While the RST input is continually held high (for more than ten
machine cycles), a forced high-to-low input transition on the PSEN# pin will bring
the device into the External Hostmode for the internal flash memory
3
programming operation.
RST
I
Reset: A high logic state on this pin for two machine cycles (at least 24 oscillator
periods), while the oscillator is running resets the device. After a successful reset
4
is completed, if the PSEN# pin is driven by an input force with a high-to-low
transition while the RST input pin is continually held high, the device will enter the
External Hostmode for the internal flash memory programming operation,
otherwise the device will enter the Normaloperation mode.
5
EA#
I
External Access Enable: EA# must be connected to VSS in order to enable the
SST89C54/58 to fetch code from External Program Memory locations starting
at 0000h up to FFFFh. Note, however, that if the Security Lock is activated on
6
either block, the logic level at EA# is internally latched during reset. EA# must be
connected to VDD for internal program execution. The EA# pin can tolerate a high
voltage2 of 12V (see Electrical Specification).
7
ALE/PROG#
I/O
Address Latch Enable: ALE is the output signal for latching the low byte of the
address during accesses to external memory. This pin is also the programming
pulse input (PROG#).
8
XTAL1
XTAL2
VDD
Vss
I
Oscillator: Input and output to the inverting oscillator amplifier. XTAL1 is input to
O
internal clock generation circuits from an external clock source.
9
I
Power Supply: Supply voltage during normal, Idle, Power Down, and Standby
Mode operations.
I
Ground: Circuit ground. (0V reference)
10
Note: 1 )
2)
I = Input
O = Output
It is not necessary to receive a 12V programming supply voltage during flash programming.
344 PGM T1.6
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© 2000 Silicon Storage Technology, Inc.
7
344-2 8/00

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