SST89C54-33-I-PI View Datasheet(PDF) - Silicon Storage Technology

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SST89C54-33-I-PI

FlashFlex51 MCU

Silicon Storage Technology 

Flash Operation Status Detection (Ext. Host

Handshake)

The SST89C54/58 provide two firmware means for an

external host to detect the completion of a flash memory

operation to optimize the Program or Erase time. The

end of a flash memory operation cycle (Erase or Pro-

gram) can be detected by: 1) monitoring the Ready/

Busy# bit at P3[3]; 2) monitoring the Data# Polling bit at

P0[7] and P0[3].

Ready/Busy# (P3[3])

The progress of the flash memory programming can be

monitored by the Ready/Busy# output signal. P3[3] is

driven low, some time after ALE/PROG# goes low during

a flash memory operation to indicate the Busy# status of

the Flash Control Unit (FCU). P3[3] is driven high when

the Flash programming operation is completed to indi-

cate the Ready status.

During a Burst-Program operation, P3[3] is driven high

(Ready) in between each byte-programmed among the

burst to indicate the ready status to receive the next byte.

When the external host detects the Ready status after a

byte among the burst is programmed, it shall then put the

data/address (within the same page) of the next byte on

the bus and drive ALE/PROG# low (pulse), before the

time-out limit expires. See Table 7 for details. Burst-

Program command presented after time-out will wait

until next cycle. Therefore, it will have longer program-

ming time.

FlashFlex51 MCU

SST89C54 / SST89C58

Preliminary Specifications

Data# Polling (P0[7] & P0[3]

During a Program operation, any attempts to read (Byte-

Verify), while the device is busy, will receive the comple-

ment of the data of the last byte loaded (logic low, i.e. “0”

for an erase) on P0[3] and P0[7] with the rest of the bits

“0”. During a Program operation, the Byte-Verify com-

mand is reading the data of the last byte loaded, not the

data at the address specified.

The true data will be read from P0[7], when the device

completes each byte programmed among the burst to

indicate the Ready status to receive the next byte. When

the external host detects the Ready status after a byte

among the burst is programmed, it should then put the

data/address (in the same page) of the next byte on the

bus and drive ALE/PROG# low immediately, before the

time-out limit expires (See programming time spec. in

Table 7 for details.). The true data will be read from P0[3],

when the Burst-Program command is terminated and the

device is ready for the next operation.

The termination of the Burst-Program can be accom-

plished by: 1) Change to a new X-Addresses (Note: the

X-Address range are different for the 4Kx8 flash Block 1

and for the 16/32K x 8 flash Block 0.); 2) Change to a new

command that requires a high to low transition of the ALE/

PROG# (i.e. any Erase or Program command); 3) Wait

for time out limit expires (20 µs); when programming the

next byte.

Flash Memory Programming with External Host Mode (Figures 10-16)

TSU

RST

TES

PSEN#

ALE/PROG#

EA#

P2[7:6] ,P3[7:6]

P3[5:4] ,P2[5:0] ,P1

P0

TRD

0000b

0030h

BFh

FIGURE 10: READ-ID

Read chip signature and identification registers at the addressed location.

© 2000 Silicon Storage Technology, Inc.

22

TRD

0000b

0031h

E4h/E2h

344 ILL F02.5

344-2 8/00

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