SST89E554RC View Datasheet(PDF) - Silicon Storage Technology

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SST89E554RC

FlashFlex51 MCU

Silicon Storage Technology 

FlashFlex51 MCU

SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC

Preliminary Specifications

TABLE 2-1: PIN DESCRIPTIONS (CONTINUED) (2 OF 2)

Symbol

Type1

Name and Functions

P3[3]

I

INT1#: External Interrupt 1 Input

P3[4]

I

T0: External count input to Timer/Counter 0

P3[5]

I

T1: External count input to Timer/Counter 1

P3[6]

O

WR#: External Data Memory Write strobe

P3[7]

O

RD#: External Data Memory Read strobe

PSEN#

I/O

Program Store Enable: PSEN# is the Read strobe to External Program Store. When the

device is executing from Internal Program Memory, PSEN# is inactive (VOH). When the

device is executing code from External Program Memory, PSEN# is activated twice each

machine cycle, except when access to External Data Memory while one PSEN# activation is

skipped in each machine cycle. A forced high-to-low input transition on the PSEN# pin while

the RST input is continually held high for more than ten machine cycles will cause the device

to enter External Host mode for programming.

RST

I

Reset: While the oscillator is running, a high logic state on this pin for two machine cycles will

reset the device. After a reset, if the PSEN# pin is driven by a high-to-low input transition

while the RST input pin is held high, the device will enter the External Host mode, otherwise

the device will enter the Normal operation mode.

EA#

I

External Access Enable: EA# must be driven to VIL in order to enable the device to fetch

code from the External Program Memory. EA# must be driven to VIH for internal program exe-

cution. However, Security lock level 4 will disable EA#, and program execution is only possi-

ble from internal program memory. The EA# pin can tolerate a high voltage2 of 12V

(see “Absolute Maximum Stress Ratings” on page 51).

ALE/PROG#

I/O

Address Latch Enable: ALE is the output signal for latching the low byte of the address dur-

ing accesses to external memory. This pin is also the programming pulse input (PROG#) for

the external host mode. ALE is activated twice each machine cycle, except when access to

External Data Memory, one ALE activation is skipped in the second machine cycle. However,

if AO is set to 1, ALE is disabled. (see “Auxiliary Register (AUXR)” on page 20)

XTAL1

XTAL2

I

Oscillator: Input and output to the inverting oscillator amplifier. XTAL1 is input to internal

O

clock generation circuits from an external clock source.

VDD

I

Power Supply: Supply voltage during normal, Idle, Power Down, and Standby Mode opera-

tions.

VSS

I

Ground: Circuit ground. (0V reference)

1. I = Input; O = Output

2. It is not necessary to receive a 12V programming supply voltage during flash programming.

T2-1.0 555

©2001 Silicon Storage Technology, Inc.

9

S71207-00-000 9/01 555

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