CY62146EV30LL View Datasheet(PDF) - Cypress Semiconductor
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CY62146EV30LL Datasheet PDF : 18 Pages
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CY62146EV30 MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled) [22, 23, 24]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tSA
WE
tPWE
BHE/BLE
OE
DATA I/O
ADDRESS
CE
WE
BHE/BLE
tBW
NOTE 25
tHZOE
tSD
tHD
DATAIN
Figure 8. Write Cycle No. 2 (CE Controlled) [22, 23, 24]
tWC
tSCE
tSA
tAW
tHA
tPWE
tBW
OE
DATA I/O NOTE 25
tHZOE
tSD
tHD
DATAIN
Notes
22.
The internal write time of the memory is defined by the
signals can terminate a write by going INACTIVE. The
overlap of
data input
WseEtu, pCEan=dVhIoL,ldBtHimEinagndm/oursBt bLeE
r=efVeIrLe.nAclel dsigtonathlse
must be
edge of
ACTIVE to initiate a write and
the signal that terminates the
any of
write.
these
23. Data I/O is high impedance if OE = VIH.
24. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
25. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 38-05567 Rev. *H
Page 9 of 18
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