ADUC814ARU(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
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ADUC814ARU
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
ADUC814ARU Datasheet PDF : 16 Pages
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ADuC814
TIMING SPECIFICATIONS (continued)
Parameter
Min
Typ
Max
Unit
SPI MASTER MODE TIMING (CPHA = 0)
tSL
tSH
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
SCLOCK Low Pulsewidth*
SCLOCK High Pulsewidth*
Data Output Valid after SCLOCK Edge
Data Output Setup before SCLOCK Edge
Data Input Setup Time before SCLOCK Edge 100
Data Input Hold Time after SCLOCK Edge
100
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
630
ns
630
ns
50
ns
150
ns
ns
ns
10
25
ns
10
25
ns
10
25
ns
10
25
ns
*Characterized under the following conditions:
a. Core clock divider Bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 MHz.
b. SPI bit rate selection Bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.
Figure
5
5
5
5
5
5
5
5
5
5
SCLOCK
(CPOL = 0)
SCLOCK
(CPOL = 1)
MOSI
MISO
tSH
tSL
tDOSU
MSB
tDAV
tDF
tDR
BITS 6–1
tSR
tSF
LSB
MSB IN
BITS 6–1
LSB IN
tDSU tDHD
Figure 5. SPI Master Mode Timing (CPHA = 0)
–10–
REV. 0
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