ADUC812 View Datasheet(PDF) - Analog Devices
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ADUC812 Datasheet PDF : 60 Pages
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ARCHITECTURE, MAIN FEATURES
The ADuC812 is a highly integrated, true 12-bit data acquisi-
tion system. At its core, the ADuC812 incorporates a high
performance 8-bit (8052 compatible) MCU with on-chip
reprogrammable nonvolatile Flash program memory control-
ling a multichannel (eight input channels) 12-bit ADC.
The chip incorporates all secondary functions to fully support
the programmable data acquisition core. These secondary
functions include User Flash Memory, Watchdog Timer
(WDT), Power Supply Monitor (PSM), and various industry-
standard parallel and serial interfaces.
PROGRAM MEMORY SPACE
READ ONLY
FFFFH
EXTERNAL
PROGRAM
MEMORY
SPACE
2000H
EA = 1
INTERNAL
8K BYTE
FLASH/EE
PROGRAM
MEMORY
1FFFH
0000H
EA = 0
EXTERNAL
PROGRAM
MEMORY
SPACE
DATA MEMORY SPACE
READ/WRITE
9FH
(PAGE 159)
640 BYTES
FLASH/EE DATA
MEMORY
ACCESSED
INDIRECTLY
VIA SFR
CONTROL REGISTERS
00H
(PAGE 0)
FFFFFFH
INTERNAL
DATA MEMORY
SPACE
FFH
UPPER
128
80H
7FH
LOWER
128
00H
ACCESSIBLE
BY
INDIRECT
ADDRESSING
ONLY
ACCESSIBLE
BY
DIRECT
AND
INDIRECT
ADDRESSING
SPECIAL FFH
FUNCTION
REGISTERS
ACCESSIBLE
BY DIRECT
ADDRESSING
ONLY
80H
000000H
EXTERNAL
DATA
MEMORY
SPACE
(24-BIT
ADDRESS
SPACE)
Figure 1. Program and Data Memory Maps
The lower 128 bytes of internal data memory are mapped as
shown in Figure 2. The lowest 32 bytes are grouped into four
banks of eight registers addressed as R0 through R7. The next
16 bytes (128 bits) above the register banks form a block of
bit addressable memory space at bit addresses 00H through 7FH.
ADuC812
7FH
BANKS
SELECTED
VIA
BITS IN PSW
20H
11
18H
10
10H
01
08H
00
00H
2FH
BIT ADDRESSABLE SPACE
(BIT ADDRESSES 0FH–7FH)
1FH
17H
4 BANKS OF 8 REGISTERS
0FH
R0–R7
07H
RESET VALUE OF
STACK POINTER
Figure 2. Lower 128 Bytes of Internal RAM
MEMORY ORGANIZATION
As with all 8052 compatible devices, the ADuC812 has separate
address spaces for program and data memory as shown in Fig-
ure 1. Also as shown in Figure 1, an additional 640 bytes of
User Data Flash EEPROM are available to the user. The User
Data Flash Memory area is accessed indirectly via a group of
control registers mapped in the Special Function Register (SFR)
area in the Data Memory Space.
The SFR space is mapped in the upper 128 bytes of internal data
memory space. The SFR area is accessed by direct addressing
only and provides an interface between the CPU and all on-chip
peripherals. A block diagram showing the programming model
of the ADuC812 via the SFR area is shown in Figure 3.
8K BYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE PROGRAM
MEMORY
640-BYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE DATA
MEMORY
8051
COMPATIBLE
CORE
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
AUTOCALIBRATING
8-CHANNEL
HIGH SPEED
12-BIT ADC
OTHER ON-CHIP
PERIPHERALS
TEMPERATURE
SENSOR
2 ؋ 12-BIT DACs
SERIAL I/O
PARALLEL I/O
WDT
PSM
Figure 3. Programming Model
REV. E
–9–
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