ADUC812 View Datasheet(PDF) - Analog Devices
Part Name
Description
View to exact match
ADUC812 Datasheet PDF : 60 Pages
| |||
USER INTERFACE TO OTHER ON-CHIP ADuC812
PERIPHERALS
The following section gives a brief overview of the various
peripherals also available on-chip. A summary of the SFRs used
to control and configure these peripherals is also given.
DAC
The ADuC812 incorporates two 12-bit voltage output DACs
on-chip. Each has a rail-to-rail voltage output buffer capable
DACCON
SFR Address
Power-On Default Value
Bit Addressable
DAC Control
Register
FDH
04H
No
MODE
RNG1
RNG0
CLR1
ADuC812
of driving 10 kΩ/100 pF. Each has two selectable ranges, 0 V to
VREF (the internal band gap 2.5 V reference) and 0 V to AVDD.
Each can operate in 12-bit or 8-bit mode. Both DACs share a
control register, DACCON, and four data registers, DAC1H/L,
DAC0H/L. It should be noted that in 12-bit asynchronous mode,
the DAC voltage output will be updated as soon as the DACL
data SFR has been written; therefore, the DAC data registers
should be updated as DACH first, followed by DACL.
CLR0
SYNC
PD1
PD0
Bit Name
7
MODE
6
RNG1
5
RNG0
4
CLR1
3
CLR0
2
SYNC
1
PD1
0
PD0
Table VIII. DACCON SFR Bit Designations
Description
The DAC MODE bit sets the overriding operating mode for both DACs.
Set to “1” = 8-bit mode (Write eight Bits to DACxL SFR).
Set to “0” = 12-bit mode.
DAC1 Range Select Bit.
Set to “1” = DAC1 range 0–VDD.
Set to “0” = DAC1 range 0–VREF.
DAC0 Range Select Bit.
Set to “1” = DAC0 range 0–VDD.
Set to “0” = DAC0 range 0–VREF.
DAC1 Clear Bit.
Set to “0” = DAC1 output forced to 0 V.
Set to “1” = DAC1 output normal.
DAC0 Clear Bit.
Set to “0” = DAC1 output forced to 0 V.
Set to “1” = DAC1 output normal.
DAC0/1 Update Synchronization Bit.
When set to “1” the DAC outputs update as soon as DACxL SFRs are written. The user can
simultaneously update both DACs by first updating the DACxL/H SFRs while SYNC is “0.” Both
DACs will then update simultaneously when the SYNC bit is set to “1.”
DAC1 Power-Down Bit.
Set to “1” = Power-on DAC1.
Set to “0” = Power-off DAC1.
DAC0 Power-Down Bit.
Set to “1” = Power-on DAC0.
Set to “0” = Power-off DAC0.
DACxH/L
Function
SFR Address
Power-On Default Value
Bit Addressable
DAC Data Registers
DAC data registers, written by user to update the DAC output.
DAC0L (DAC0 Data Low Byte) ➝F9H; DAC1L (DAC1 data low byte)➝FBH
DAC0H (DAC0 Data High Byte) ➝FAH; DAC1H(DAC1 data high byte)➝FCH
00H
➝All four registers
No
➝All four registers
The 12-bit DAC data should be written into DACxH/L, right-justified such that DACL contains the lower eight bits, and the lower
nibble of DACH contains the upper four bits.
REV. E
–21–
Share Link: 