ADUC812_03 View Datasheet(PDF) - Analog Devices
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ADUC812_03 Datasheet PDF : 60 Pages
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ADuC812
OVERVIEW OF MCU-RELATED SFRs
Accumulator SFR
ACC is the Accumulator register and is used for math opera-
tions including addition, subtraction, integer multiplication and
division, and Boolean bit manipulations. The mnemonics for
accumulator-specific instructions refer to the Accumulator as A.
B SFR
The B register is used with the ACC for multiplication and
division operations. For other instructions, it can be treated as a
general-purpose scratch pad register.
Stack Pointer SFR
The SP register is the stack pointer and is used to hold an internal
RAM address that is called the “top of the stack.” The SP register
is incremented before data is stored during PUSH and CALL
executions. While the stack may reside anywhere in on-chip RAM,
the SP register is initialized to 07H after a reset. This causes the
stack to begin at location 08H.
Data Pointer
The Data Pointer is made up of three 8-bit registers: DPP (page
byte), DPH (high byte), and DPL (low byte). These are used to
provide memory addresses for internal and external code access
and external data access. It may be manipulated as a 16-bit
register (DPTR = DPH, DPL), although INC DPTR instructions
will automatically carry over to DPP, or as three independent
8-bit registers (DPP, DPH, and DPL).
Program Status Word SFR
The PSW register is the Program Status Word that contains
several bits reflecting the current status of the CPU as detailed
in Table I.
SFR Address
Power-On Default Value
Bit Addressable
D0H
00H
Yes
Power Control SFR
The Power Control (PCON) register contains bits for power
saving options and general-purpose status flags as shown in
Table II.
SFR Address
87H
Power-On Default Value
00H
Bit Addressable
No
SMOD SERIPD INTOPD ALEOFF GF1 GF0 PD IDL
Table II. PCON SFR Bit Designations
Bit Name
7
SMOD
6
———
5
———
4
ALEOFF
3
GF1
2
GF0
1
PD
0
IDL
Description
Double UART Baud Rate
Reserved
Reserved
Disable ALE Output
General-Purpose Flag Bit
General-Purpose Flag Bit
Power-Down Mode Enable
Idle Mode Enable
CY
AC
F0
RS1 RS0 OV F1
P
Table I. PSW SFR Bit Designations
Bit
Name
Description
7
CY
6
AC
5
F0
4
RS1
3
RS0
2
OV
1
F1
0
P
Carry Flag
Auxiliary Carry Flag
General-Purpose Flag
Register Bank Select Bits
RS1 RS0 Selected Bank
0
0
0
0
1
1
1
0
2
1
1
3
Overflow Flag
General-Purpose Flag
Parity Bit
–10–
REV. E
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