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ICL7641E View Datasheet(PDF) - Intersil

Part Name
Description
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ICL7641E Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
ICL7621, ICL7641, ICL7642
Electrical Specifications VSUPPLY = ±5V, Unless Otherwise Specified (Continued)
PARAMETER
Input Referred Noise Voltage
Input Referred Noise Current
Supply Current (Per Amplifier)
(No Signal, No Load)
Channel Separation
Slew Rate (AV = 1, CL = 100pF,
VIN = 8VP-P)
Rise Time
(VIN = 50mV, CL = 100pF)
Overshoot Factor
(VIN = 50mV, CL = 100pF)
SYMBOL
eN
iN
ISUPPLY
VO1/VO2
SR
tR
OS
TEST
CONDITIONS
RS = 100, f = 1kHz
RS = 100, f = 1kHz
ICL7642, IQ = 10µA Low Bias
ICL7641, IQ = 1mA High Bias
AV = 100
ICL7642, IQ = 10µA, RL = 1M
ICL7641, IQ = 1mA, RL = 10k
ICL7642, IQ = 10µA, RL = 1M
ICL7641, IQ = 1mA, RL = 10k
ICL7642, IQ = 10µA, RL = 1M
ICL7641, IQ = 1mA, RL = 10k
TEMP.
(oC)
25
25
25
25
25
25
25
25
25
25
25
ICL7641E, ICL7642E
MIN TYP
MAX
-
100
-
-
0.01
-
-
0.01
0.03
-
1.0
2.5
-
120
-
-
0.016
-
-
1.6
-
-
20
-
-
0.9
-
-
5
-
-
40
-
Schematic Diagram
INPUT STAGE
IQ
SETTING STAGE
OUTPUT STAGE
+INPUT
3K
3K
QP1
V+
QP2
QN1 QN2
900K
QP5
100K
QP3
QP4
V-
V+
V+
A
C
V-
QP6
QP7
QP8
6.3V
QP9
CFF = 9pF
CC = 33pF
OUTPUT
UNITS
nV/Hz
pA/Hz
mA
mA
dB
V/µs
V/µs
µs
µs
%
%
-INPUT
QN7
QN9
V-
QN4
QN6
QN10
QN11
QN5
6.3V
TABLE OF JUMPERS
IQ
QN3
V+
E
ICL7621
C, E
100µA
QN8
G
V-
ICL7641
C, G 1mA
ICL7642
A, E
10µA
Application Information
Static Protection
All devices are static protected by the use of input diodes.
However, strong static fields should be avoided, as it is
possible for the strong fields to cause degraded diode
junction characteristics, which may result in increased input
leakage currents.
Latchup Avoidance
Junction-isolated CMOS circuits employ configurations
which produce a parasitic 4-layer (PNPN) structure. The
4
4-layer structure has characteristics similar to an SCR, and
under certain circumstances may be triggered into a low
impedance state resulting in excessive supply current. To
avoid this condition, no voltage greater than 0.3V beyond the
supply rails may be applied to any pin. In general, the op
amp supplies must be established simultaneously with, or
before any input signals are applied. If this is not possible,
the drive circuits must limit input current flow to 2mA to
prevent latchup.

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