xr
SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
FIGURE 5. MICROPROCESSOR INTERFACE TIMING
CS
MODE 1
MODE 2
EC1
EC2
EC3
LOOPA
LLOPB
t1
t3
t4
XRT83D10
REV. 1.0.3
t2
t5
SYMBOL
t1
t2
t3
t4
t5
TABLE 5: MICROPROCESSOR INTERFACE TIMING
PARAMETER
MIN
Control Signal Rise Time (10% - 90%)
Control Signal Rise Time (10% - 90%)
Control Signal Pulse Width Time
40
Control SIgnal Setup Time
50
Control Signal Hold Time
40
MAX
40
40
UNIT
ns
ns
ns
ns
ns
9