XR16C850IJ View Datasheet(PDF) - Exar Corporation

Part Name

Description

View to exact match

XR16C850IJ

UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control

Exar Corporation 

XR16C850

SYMBOL DESCRIPTION

Symbol

BUS8/16

CLK8/16

DRQ

-DACK

-DDIS

GND

INT

-IOR

-IOW

IRQA / INT

Pin

Signal

40 44 48 52 type

Pin Description

is framing error bit and D12 is the break bit.

-

-

25 28

I

8 or 16 Bit Bus select (internal pull-up). For normal

8 bit data bus operation this pin should be connected

to VCC. Connect this pin to GND for 16 bit data bus

operation where RX data errors (parity, framing and

break) are presented on the data bus as D10, D11

and D12 along with the data byte.

-

-

-

27

I

Transmit / Receive data sampling clock rate (inter-

nal pull-up). For normal operation this pin should be

connected to VCC for 16X sampling clock (stan-

dard). Connect to GND for 8X sampling to double the

data rates.

-

-

-

32

O Receive DMA Request. A Receive ready request is

generated by bringing a RxDRQ line to a high level.

DRQ line is held high until the corresponding DMA

acknowledge (-DACK) line goes low.

-

-

-

46

I

DMA Acknowledge Bit (internal pull-up). DMA cycle

will start processing when CPU/Host sets this input

to low. Connect this pin to VCC when not used.

(See LPT-2)

20 22 18 19 Pwr Signal and Power Ground.

(See IRQA)

21 24 19 21

I

Input/Output Read (active low strobe). A logic 0 on

this pin transfers the contents of the 850 data bus to

the CPU. Connect this pin to VCC when IOR is used.

18 20 16 17

I

Input/Output Write (active low strobe) - A logic 0 on

this pin transfers the contents of the CPU data bus

to the addressed internal register. Connect this pin

to VCC when IOW is used.

30

33

30

33

O Interrupt Request “A” or Interrupt (three state, open

source, active high) - During PC mode of operation,

this pin functions as IRQA. IRQA is enabled when

Rev. 1.20

7

Share Link: