SAA7500 View Datasheet(PDF) - Philips Electronics

Part Name

Description

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SAA7500

Digital satellite radio broadcasting tuner decoder (SAT-2)

Philips Electronics 

Philips Semiconductors

Digital satellite radio broadcasting tuner

decoder (SAT-2)

Product specification

SAA7500

Digital-to-analogue conversion and interfaces

The SAA7500 enables different DAC systems to be used. For control of the SAA7220P/C and TDA1541 a 2.5 external

divider must be connected to the 20.48 MHz clock signal to produce the required 8.192 MHz clock signal.

A serial interface is built in with the following outputs: bit clock (AWT), word select (AWR) and audio data (AWD).

In addition the mute signal (AMUN) and the concealment flag (ACM) are also available. The SAA7220P/C and TDA1541

are equipped with a digital audio interface for domestic use equivalent to ‘IEC proposal No. 84 (secretariat 28; from June

1985)’.

For DACs with a parallel interface in a multiplex mode the audio data are available at the B1(MSB)-B16 outputs.

The multiplexing is controlled by the L32 and R32 outputs. Using the mode outputs DWCA and DWCB the code (offset

binary or two’s complement) and polarity can be selected.

Additional information, including the scale factor is available through the programme information (PI) interface (PID,

PITN, and PIF). Another interface, using the ASC, BSC and T10N outputs, makes available signals from the differential

decoder. These signals are used for bit error measurement and an optimized phase adjustment of the internal clock (refer

to ‘clock recovery’ section).

An optional application of the control signals for mute and concealment operations is possible using the outputs AMUN

and ACM. For the mute signal a different time relationship to the unwanted pulse with very low C/N values may be

obtained.

The external application of the concealment signal is recommended; if an additional interpolation is required between

additional samples with different levels in the external circuitry (such as the SAA7220P/C).

Truth tables

Table 1 Delay adjustment

pins 1 to 3

LZC

0

0

0

0

1

1

1

1

LZB

0

0

1

1

0

0

1

1

LZA

0

1

0

1

0

1

0

1

DELAY

4×τ

3×τ

2×τ

1×τ

0×τ

−1 × τ

−2 × τ

−3 × τ

Table 2 Master reset

pin 64

MCR

0

1

Table 3 Mute

pin 16

UPMU

0

1

FUNCTION

operation

master reset

FUNCTION

no

yes

τ ≈ 1.5 × gate delay time (NAND)

September 1989

9

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