WM8580 View Datasheet(PDF) - Wolfson Microelectronics plc

Part Name

Description

View to exact match

WM8580

Multichannel CODEC with S/PDIF Transceiver

Wolfson Microelectronics plc 

WM8580

DIGITAL AUDIO INTERFACE – SLAVE MODE

tBCH

tBCL

PAIFTX_BCLK/

PAIFRX_BCLK/

SAIF_BCLK

tBCY

PAIFTX_LRCLK/

PAIFRX_LRCLK/

SAIF_BCLK

DIN1/2/3/

SAIF_DIN

tDS

tDD

DOUT/

SAIF_DOUT

tLRH

tDH

tLRSU

Production Data

Figure 3 Digital Audio Data Timing – Slave Mode

Test Conditions

AVDD, PVDD = 5V, DVDD = 3.3V, AGND = 0V, PGND,DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK and

ADCMCLK = 256fs unless otherwise stated.

PARAMETER

SYMBOL

Audio Data Input Timing Information

PAIFTX_BCLK/

tBCY

PAIFRX_BCLK/SAIF_BCLK cycle

time

PAIFTX_BCLK/

tBCH

PAIFRX_BCLK/SAIF_BCLK pulse

width high

PAIFTX_BCLK/

tBCL

PAIFRX_BCLK/SAIF_BCLK pulse

width low

PAIFTX_LRCLK/

PAIFRX_LRCLK/SAIF_BCLK set-up

time to PAIFTX_BCLK/

tLRSU

PAIFRX_BCLK/SAIF_BCLK rising

edge

PAIFTX_LRCLK/

tLRH

PAIFRX_LRCLK/

SAIF_LRCLK hold time from

PAIFTX_BCLK/

PAIFRX_BCLK/SAIF_BCLK rising

edge

DIN1/2/3/SAIF_DIN set-up time to

tDS

PAIFRX_BCLK/

SAIF_BCLK rising edge

DIN1/2/3/SAIF_DIN hold time from

tDH

PAIFRX_BCLK/SAIF_BCLK rising

edge

DOUT/SAIF_DOUT propagation

tDD

delay from

PAIFTX_BCLK/SAIF_BCLK falling

edge

Table 5 Digital Audio Data Timing – Slave Mode

TEST CONDITIONS

MIN

TYP

MAX

UNIT

50

ns

20

ns

20

ns

10

ns

10

ns

10

ns

10

ns

0

10

ns

w

PD Rev 4.3 August 2007

14

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