WM8746 View Datasheet(PDF) - Wolfson Microelectronics plc
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WM8746 Datasheet PDF : 32 Pages
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WM8746
MASTER CLOCK TIMING
Production Data
SCKI
tSCKIL
tSCKIH
tSCKIY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
System Clock Timing Information
SCKI System clock pulse width high
tSCKIH
SCKI System clock pulse width low
tSCKIL
SCKI System clock cycle time
tSCKIY
SCKI Duty cycle
TEST CONDITIONS
MIN
13
13
26
40:60
TYP
MAX
60:40
Table 1 Master Clock Timing Requirements
UNIT
ns
ns
ns
DIGITAL AUDIO INTERFACE TIMING
BCLK
tBCH
tBCL
tBCY
DACLRC
DIN0/1/2
tDS
tLRH
tLRSU
tDH
Figure 2 PCM Digital Audio Data Timing
Test Conditions
AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
BCKIN cycle time
tBCY
BCKIN pulse width high
tBCH
BCKIN pulse width low
tBCL
LRCIN set-up time to
tLB
BCKIN rising edge
LRCIN hold time from
tBL
BCKIN rising edge
DIN0/1/2 set-up time to
tDS
BCKIN rising edge
DIN0/1/2 hold time from
tDH
BCKIN rising edge
TEST CONDITIONS
MIN
TYP
MAX
40
16
16
8
8
8
8
Table 2 PCM Digital Audio Timing
UNIT
ns
ns
ns
ns
ns
ns
ns
w
March 2006, PD Rev 4.0
8
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